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[RISCV][GISel] Remove s32 support on RV64 for DIV, and REM. (#102519)
Based on experience with SelectionDAG and experimental-rv64-legal-i32, I don't believe making s32 a legal type is viable without introducing an invariant that s32 values are always sign extended like Mips64 does. Mips64 does this with a separate 32-bit register class. `experimental-rv64-legal-i32` was removed in ##102509. This patch is part of a series to remove s32 support so we can remove the isel patterns that SelectionDAG is no longer using. To restore code quality, we will need to add custom W nodes like SelectionDAG.
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-293
lines changed

5 files changed

+122
-293
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‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -407,9 +407,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
407407

408408
if (ST.hasStdExtM()) {
409409
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM})
410-
.legalFor({s32, sXLen})
410+
.legalFor({sXLen})
411411
.libcallFor({sDoubleXLen})
412-
.clampScalar(0, s32, sDoubleXLen)
412+
.clampScalar(0, sXLen, sDoubleXLen)
413413
.widenScalarToNextPow2(0);
414414
} else {
415415
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM})

‎llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -348,7 +348,9 @@ define i32 @sdiv_i32(i32 %a, i32 %b) {
348348
;
349349
; RV64IM-LABEL: sdiv_i32:
350350
; RV64IM: # %bb.0: # %entry
351-
; RV64IM-NEXT: divw a0, a0, a1
351+
; RV64IM-NEXT: sext.w a0, a0
352+
; RV64IM-NEXT: sext.w a1, a1
353+
; RV64IM-NEXT: div a0, a0, a1
352354
; RV64IM-NEXT: ret
353355
entry:
354356
%0 = sdiv i32 %a, %b
@@ -363,7 +365,9 @@ define i32 @srem_i32(i32 %a, i32 %b) {
363365
;
364366
; RV64IM-LABEL: srem_i32:
365367
; RV64IM: # %bb.0: # %entry
366-
; RV64IM-NEXT: remw a0, a0, a1
368+
; RV64IM-NEXT: sext.w a0, a0
369+
; RV64IM-NEXT: sext.w a1, a1
370+
; RV64IM-NEXT: rem a0, a0, a1
367371
; RV64IM-NEXT: ret
368372
entry:
369373
%0 = srem i32 %a, %b
@@ -378,7 +382,11 @@ define i32 @udiv_i32(i32 %a, i32 %b) {
378382
;
379383
; RV64IM-LABEL: udiv_i32:
380384
; RV64IM: # %bb.0: # %entry
381-
; RV64IM-NEXT: divuw a0, a0, a1
385+
; RV64IM-NEXT: slli a0, a0, 32
386+
; RV64IM-NEXT: srli a0, a0, 32
387+
; RV64IM-NEXT: slli a1, a1, 32
388+
; RV64IM-NEXT: srli a1, a1, 32
389+
; RV64IM-NEXT: divu a0, a0, a1
382390
; RV64IM-NEXT: ret
383391
entry:
384392
%0 = udiv i32 %a, %b
@@ -393,7 +401,11 @@ define i32 @urem_i32(i32 %a, i32 %b) {
393401
;
394402
; RV64IM-LABEL: urem_i32:
395403
; RV64IM: # %bb.0: # %entry
396-
; RV64IM-NEXT: remuw a0, a0, a1
404+
; RV64IM-NEXT: slli a0, a0, 32
405+
; RV64IM-NEXT: srli a0, a0, 32
406+
; RV64IM-NEXT: slli a1, a1, 32
407+
; RV64IM-NEXT: srli a1, a1, 32
408+
; RV64IM-NEXT: remu a0, a0, a1
397409
; RV64IM-NEXT: ret
398410
entry:
399411
%0 = urem i32 %a, %b

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir

Lines changed: 0 additions & 135 deletions
Original file line numberDiff line numberDiff line change
@@ -2,141 +2,6 @@
22
# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
33
# RUN: | FileCheck -check-prefix=RV64I %s
44

5-
---
6-
name: mul_i32
7-
legalized: true
8-
regBankSelected: true
9-
tracksRegLiveness: true
10-
body: |
11-
bb.0.entry:
12-
liveins: $x10, $x11
13-
14-
; RV64I-LABEL: name: mul_i32
15-
; RV64I: liveins: $x10, $x11
16-
; RV64I-NEXT: {{ $}}
17-
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19-
; RV64I-NEXT: [[MULW:%[0-9]+]]:gpr = MULW [[COPY]], [[COPY1]]
20-
; RV64I-NEXT: $x10 = COPY [[MULW]]
21-
; RV64I-NEXT: PseudoRET implicit $x10
22-
%0:gprb(s64) = COPY $x10
23-
%1:gprb(s32) = G_TRUNC %0(s64)
24-
%2:gprb(s64) = COPY $x11
25-
%3:gprb(s32) = G_TRUNC %2(s64)
26-
%4:gprb(s32) = G_MUL %1, %3
27-
%5:gprb(s64) = G_ANYEXT %4(s32)
28-
$x10 = COPY %5(s64)
29-
PseudoRET implicit $x10
30-
31-
...
32-
---
33-
name: sdiv_i32
34-
legalized: true
35-
regBankSelected: true
36-
tracksRegLiveness: true
37-
body: |
38-
bb.0.entry:
39-
liveins: $x10, $x11
40-
41-
; RV64I-LABEL: name: sdiv_i32
42-
; RV64I: liveins: $x10, $x11
43-
; RV64I-NEXT: {{ $}}
44-
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
45-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
46-
; RV64I-NEXT: [[DIVW:%[0-9]+]]:gpr = DIVW [[COPY]], [[COPY1]]
47-
; RV64I-NEXT: $x10 = COPY [[DIVW]]
48-
; RV64I-NEXT: PseudoRET implicit $x10
49-
%0:gprb(s64) = COPY $x10
50-
%1:gprb(s32) = G_TRUNC %0(s64)
51-
%2:gprb(s64) = COPY $x11
52-
%3:gprb(s32) = G_TRUNC %2(s64)
53-
%4:gprb(s32) = G_SDIV %1, %3
54-
%5:gprb(s64) = G_ANYEXT %4(s32)
55-
$x10 = COPY %5(s64)
56-
PseudoRET implicit $x10
57-
58-
...
59-
---
60-
name: srem_i32
61-
legalized: true
62-
regBankSelected: true
63-
tracksRegLiveness: true
64-
body: |
65-
bb.0.entry:
66-
liveins: $x10, $x11
67-
68-
; RV64I-LABEL: name: srem_i32
69-
; RV64I: liveins: $x10, $x11
70-
; RV64I-NEXT: {{ $}}
71-
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
72-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
73-
; RV64I-NEXT: [[REMW:%[0-9]+]]:gpr = REMW [[COPY]], [[COPY1]]
74-
; RV64I-NEXT: $x10 = COPY [[REMW]]
75-
; RV64I-NEXT: PseudoRET implicit $x10
76-
%0:gprb(s64) = COPY $x10
77-
%1:gprb(s32) = G_TRUNC %0(s64)
78-
%2:gprb(s64) = COPY $x11
79-
%3:gprb(s32) = G_TRUNC %2(s64)
80-
%4:gprb(s32) = G_SREM %1, %3
81-
%5:gprb(s64) = G_ANYEXT %4(s32)
82-
$x10 = COPY %5(s64)
83-
PseudoRET implicit $x10
84-
85-
...
86-
---
87-
name: udiv_i32
88-
legalized: true
89-
regBankSelected: true
90-
tracksRegLiveness: true
91-
body: |
92-
bb.0.entry:
93-
liveins: $x10, $x11
94-
95-
; RV64I-LABEL: name: udiv_i32
96-
; RV64I: liveins: $x10, $x11
97-
; RV64I-NEXT: {{ $}}
98-
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
99-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
100-
; RV64I-NEXT: [[DIVUW:%[0-9]+]]:gpr = DIVUW [[COPY]], [[COPY1]]
101-
; RV64I-NEXT: $x10 = COPY [[DIVUW]]
102-
; RV64I-NEXT: PseudoRET implicit $x10
103-
%0:gprb(s64) = COPY $x10
104-
%1:gprb(s32) = G_TRUNC %0(s64)
105-
%2:gprb(s64) = COPY $x11
106-
%3:gprb(s32) = G_TRUNC %2(s64)
107-
%4:gprb(s32) = G_UDIV %1, %3
108-
%5:gprb(s64) = G_ANYEXT %4(s32)
109-
$x10 = COPY %5(s64)
110-
PseudoRET implicit $x10
111-
112-
...
113-
---
114-
name: urem_i32
115-
legalized: true
116-
regBankSelected: true
117-
tracksRegLiveness: true
118-
body: |
119-
bb.0.entry:
120-
liveins: $x10, $x11
121-
122-
; RV64I-LABEL: name: urem_i32
123-
; RV64I: liveins: $x10, $x11
124-
; RV64I-NEXT: {{ $}}
125-
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
126-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
127-
; RV64I-NEXT: [[REMUW:%[0-9]+]]:gpr = REMUW [[COPY]], [[COPY1]]
128-
; RV64I-NEXT: $x10 = COPY [[REMUW]]
129-
; RV64I-NEXT: PseudoRET implicit $x10
130-
%0:gprb(s64) = COPY $x10
131-
%1:gprb(s32) = G_TRUNC %0(s64)
132-
%2:gprb(s64) = COPY $x11
133-
%3:gprb(s32) = G_TRUNC %2(s64)
134-
%4:gprb(s32) = G_UREM %1, %3
135-
%5:gprb(s64) = G_ANYEXT %4(s32)
136-
$x10 = COPY %5(s64)
137-
PseudoRET implicit $x10
138-
139-
...
1405
---
1416
name: mul_i64
1427
legalized: true

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir

Lines changed: 52 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -28,19 +28,14 @@ body: |
2828
; CHECK-M-LABEL: name: sdiv_i8
2929
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
3030
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
31-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
32-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
33-
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
34-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
35-
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
36-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
37-
; CHECK-M-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
38-
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s64)
39-
; CHECK-M-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
40-
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C3]](s64)
41-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
42-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
43-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
31+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
32+
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
33+
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
34+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
35+
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
36+
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
37+
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
38+
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
4439
; CHECK-M-NEXT: PseudoRET implicit $x10
4540
%0:_(s64) = COPY $x10
4641
%1:_(s64) = COPY $x11
@@ -77,19 +72,14 @@ body: |
7772
; CHECK-M-LABEL: name: sdiv_i15
7873
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
7974
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
80-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
81-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
82-
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
83-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
84-
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
85-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
86-
; CHECK-M-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
87-
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s64)
88-
; CHECK-M-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
89-
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C3]](s64)
90-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
91-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
92-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
75+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
76+
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
77+
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
78+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
79+
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
80+
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
81+
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
82+
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
9383
; CHECK-M-NEXT: PseudoRET implicit $x10
9484
%0:_(s64) = COPY $x10
9585
%1:_(s64) = COPY $x11
@@ -126,19 +116,14 @@ body: |
126116
; CHECK-M-LABEL: name: sdiv_i16
127117
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
128118
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
129-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
130-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
131-
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
132-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
133-
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
134-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
135-
; CHECK-M-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
136-
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s64)
137-
; CHECK-M-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
138-
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C3]](s64)
139-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
140-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
141-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
119+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
120+
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
121+
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
122+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
123+
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
124+
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
125+
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
126+
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
142127
; CHECK-M-NEXT: PseudoRET implicit $x10
143128
%0:_(s64) = COPY $x10
144129
%1:_(s64) = COPY $x11
@@ -171,11 +156,10 @@ body: |
171156
; CHECK-M-LABEL: name: sdiv_i32
172157
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
173158
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
174-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
175-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
176-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
177-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
178-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
159+
; CHECK-M-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
160+
; CHECK-M-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
161+
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
162+
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
179163
; CHECK-M-NEXT: PseudoRET implicit $x10
180164
%0:_(s64) = COPY $x10
181165
%1:_(s64) = COPY $x11
@@ -358,15 +342,12 @@ body: |
358342
; CHECK-M-LABEL: name: udiv_i8
359343
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
360344
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
361-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
362-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
363-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
364-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
365-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
366-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
367-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
368-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
369-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
345+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
346+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
347+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
348+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
349+
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
350+
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
370351
; CHECK-M-NEXT: PseudoRET implicit $x10
371352
%0:_(s64) = COPY $x10
372353
%1:_(s64) = COPY $x11
@@ -401,15 +382,12 @@ body: |
401382
; CHECK-M-LABEL: name: udiv_i15
402383
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
403384
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
404-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
405-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
406-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
407-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
408-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
409-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
410-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
411-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
412-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
385+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
386+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
387+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
388+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
389+
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
390+
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
413391
; CHECK-M-NEXT: PseudoRET implicit $x10
414392
%0:_(s64) = COPY $x10
415393
%1:_(s64) = COPY $x11
@@ -444,15 +422,12 @@ body: |
444422
; CHECK-M-LABEL: name: udiv_i16
445423
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
446424
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
447-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
448-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
449-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
450-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
451-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
452-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
453-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
454-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
455-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
425+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
426+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
427+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
428+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
429+
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
430+
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
456431
; CHECK-M-NEXT: PseudoRET implicit $x10
457432
%0:_(s64) = COPY $x10
458433
%1:_(s64) = COPY $x11
@@ -487,11 +462,12 @@ body: |
487462
; CHECK-M-LABEL: name: udiv_i32
488463
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
489464
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
490-
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
491-
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
492-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[TRUNC]], [[TRUNC1]]
493-
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
494-
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
465+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
466+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
467+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
468+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
469+
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
470+
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
495471
; CHECK-M-NEXT: PseudoRET implicit $x10
496472
%0:_(s64) = COPY $x10
497473
%1:_(s64) = COPY $x11

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