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tstellartstellar
committedJun 11, 2019
Merging r360862:
------------------------------------------------------------------------ r360862 | mstorsjo | 2019-05-15 23:49:20 -0700 (Wed, 15 May 2019) | 12 lines [PPC] Fix 32-bit build of libunwind Clang integrated assembler was unable to build libunwind PPC32 assembly code, present in functions used to save/restore register context. This change consists in replacing the assembly style used in libunwind source, to one that is compatible with both Clang integrated assembler as well as GNU assembler. Patch by Leandro Lupori! Differential Revision: https://reviews.llvm.org/D61792 ------------------------------------------------------------------------ llvm-svn: 363030
·
llvmorg-8.0.1llvmorg-8.0.1-rc2
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‎libunwind/src/UnwindRegistersRestore.S

Lines changed: 119 additions & 119 deletions
Original file line numberDiff line numberDiff line change
@@ -396,119 +396,119 @@ Lnovec:
396396
#elif defined(__ppc__)
397397

398398
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv)
399-
;
400-
; void libunwind::Registers_ppc::jumpto()
401-
;
402-
; On entry:
403-
; thread_state pointer is in r3
404-
;
405-
406-
; restore integral registerrs
407-
; skip r0 for now
408-
; skip r1 for now
409-
lwz r2, 16(r3)
410-
; skip r3 for now
411-
; skip r4 for now
412-
; skip r5 for now
413-
lwz r6, 32(r3)
414-
lwz r7, 36(r3)
415-
lwz r8, 40(r3)
416-
lwz r9, 44(r3)
417-
lwz r10, 48(r3)
418-
lwz r11, 52(r3)
419-
lwz r12, 56(r3)
420-
lwz r13, 60(r3)
421-
lwz r14, 64(r3)
422-
lwz r15, 68(r3)
423-
lwz r16, 72(r3)
424-
lwz r17, 76(r3)
425-
lwz r18, 80(r3)
426-
lwz r19, 84(r3)
427-
lwz r20, 88(r3)
428-
lwz r21, 92(r3)
429-
lwz r22, 96(r3)
430-
lwz r23,100(r3)
431-
lwz r24,104(r3)
432-
lwz r25,108(r3)
433-
lwz r26,112(r3)
434-
lwz r27,116(r3)
435-
lwz r28,120(r3)
436-
lwz r29,124(r3)
437-
lwz r30,128(r3)
438-
lwz r31,132(r3)
439-
440-
; restore float registers
441-
lfd f0, 160(r3)
442-
lfd f1, 168(r3)
443-
lfd f2, 176(r3)
444-
lfd f3, 184(r3)
445-
lfd f4, 192(r3)
446-
lfd f5, 200(r3)
447-
lfd f6, 208(r3)
448-
lfd f7, 216(r3)
449-
lfd f8, 224(r3)
450-
lfd f9, 232(r3)
451-
lfd f10,240(r3)
452-
lfd f11,248(r3)
453-
lfd f12,256(r3)
454-
lfd f13,264(r3)
455-
lfd f14,272(r3)
456-
lfd f15,280(r3)
457-
lfd f16,288(r3)
458-
lfd f17,296(r3)
459-
lfd f18,304(r3)
460-
lfd f19,312(r3)
461-
lfd f20,320(r3)
462-
lfd f21,328(r3)
463-
lfd f22,336(r3)
464-
lfd f23,344(r3)
465-
lfd f24,352(r3)
466-
lfd f25,360(r3)
467-
lfd f26,368(r3)
468-
lfd f27,376(r3)
469-
lfd f28,384(r3)
470-
lfd f29,392(r3)
471-
lfd f30,400(r3)
472-
lfd f31,408(r3)
473-
474-
; restore vector registers if any are in use
475-
lwz r5,156(r3) ; test VRsave
476-
cmpwi r5,0
477-
beq Lnovec
478-
479-
subi r4,r1,16
480-
rlwinm r4,r4,0,0,27 ; mask low 4-bits
481-
; r4 is now a 16-byte aligned pointer into the red zone
482-
; the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer
399+
//
400+
// void libunwind::Registers_ppc::jumpto()
401+
//
402+
// On entry:
403+
// thread_state pointer is in r3
404+
//
405+
406+
// restore integral registerrs
407+
// skip r0 for now
408+
// skip r1 for now
409+
lwz %r2, 16(%r3)
410+
// skip r3 for now
411+
// skip r4 for now
412+
// skip r5 for now
413+
lwz %r6, 32(%r3)
414+
lwz %r7, 36(%r3)
415+
lwz %r8, 40(%r3)
416+
lwz %r9, 44(%r3)
417+
lwz %r10, 48(%r3)
418+
lwz %r11, 52(%r3)
419+
lwz %r12, 56(%r3)
420+
lwz %r13, 60(%r3)
421+
lwz %r14, 64(%r3)
422+
lwz %r15, 68(%r3)
423+
lwz %r16, 72(%r3)
424+
lwz %r17, 76(%r3)
425+
lwz %r18, 80(%r3)
426+
lwz %r19, 84(%r3)
427+
lwz %r20, 88(%r3)
428+
lwz %r21, 92(%r3)
429+
lwz %r22, 96(%r3)
430+
lwz %r23,100(%r3)
431+
lwz %r24,104(%r3)
432+
lwz %r25,108(%r3)
433+
lwz %r26,112(%r3)
434+
lwz %r27,116(%r3)
435+
lwz %r28,120(%r3)
436+
lwz %r29,124(%r3)
437+
lwz %r30,128(%r3)
438+
lwz %r31,132(%r3)
439+
440+
// restore float registers
441+
lfd %f0, 160(%r3)
442+
lfd %f1, 168(%r3)
443+
lfd %f2, 176(%r3)
444+
lfd %f3, 184(%r3)
445+
lfd %f4, 192(%r3)
446+
lfd %f5, 200(%r3)
447+
lfd %f6, 208(%r3)
448+
lfd %f7, 216(%r3)
449+
lfd %f8, 224(%r3)
450+
lfd %f9, 232(%r3)
451+
lfd %f10,240(%r3)
452+
lfd %f11,248(%r3)
453+
lfd %f12,256(%r3)
454+
lfd %f13,264(%r3)
455+
lfd %f14,272(%r3)
456+
lfd %f15,280(%r3)
457+
lfd %f16,288(%r3)
458+
lfd %f17,296(%r3)
459+
lfd %f18,304(%r3)
460+
lfd %f19,312(%r3)
461+
lfd %f20,320(%r3)
462+
lfd %f21,328(%r3)
463+
lfd %f22,336(%r3)
464+
lfd %f23,344(%r3)
465+
lfd %f24,352(%r3)
466+
lfd %f25,360(%r3)
467+
lfd %f26,368(%r3)
468+
lfd %f27,376(%r3)
469+
lfd %f28,384(%r3)
470+
lfd %f29,392(%r3)
471+
lfd %f30,400(%r3)
472+
lfd %f31,408(%r3)
473+
474+
// restore vector registers if any are in use
475+
lwz %r5, 156(%r3) // test VRsave
476+
cmpwi %r5, 0
477+
beq Lnovec
483478

479+
subi %r4, %r1, 16
480+
rlwinm %r4, %r4, 0, 0, 27 // mask low 4-bits
481+
// r4 is now a 16-byte aligned pointer into the red zone
482+
// the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer
483+
484484

485485
#define LOAD_VECTOR_UNALIGNEDl(_index) \
486-
andis. r0,r5,(1<<(15-_index)) @\
487-
beq Ldone ## _index @\
488-
lwz r0, 424+_index*16(r3) @\
489-
stw r0, 0(r4) @\
490-
lwz r0, 424+_index*16+4(r3) @\
491-
stw r0, 4(r4) @\
492-
lwz r0, 424+_index*16+8(r3) @\
493-
stw r0, 8(r4) @\
494-
lwz r0, 424+_index*16+12(r3)@\
495-
stw r0, 12(r4) @\
496-
lvx v ## _index,0,r4 @\
497-
Ldone ## _index:
486+
andis. %r0, %r5, (1<<(15-_index)) SEPARATOR \
487+
beq Ldone ## _index SEPARATOR \
488+
lwz %r0, 424+_index*16(%r3) SEPARATOR \
489+
stw %r0, 0(%r4) SEPARATOR \
490+
lwz %r0, 424+_index*16+4(%r3) SEPARATOR \
491+
stw %r0, 4(%r4) SEPARATOR \
492+
lwz %r0, 424+_index*16+8(%r3) SEPARATOR \
493+
stw %r0, 8(%r4) SEPARATOR \
494+
lwz %r0, 424+_index*16+12(%r3) SEPARATOR \
495+
stw %r0, 12(%r4) SEPARATOR \
496+
lvx %v ## _index, 0, %r4 SEPARATOR \
497+
Ldone ## _index:
498498

499499
#define LOAD_VECTOR_UNALIGNEDh(_index) \
500-
andi. r0,r5,(1<<(31-_index)) @\
501-
beq Ldone ## _index @\
502-
lwz r0, 424+_index*16(r3) @\
503-
stw r0, 0(r4) @\
504-
lwz r0, 424+_index*16+4(r3) @\
505-
stw r0, 4(r4) @\
506-
lwz r0, 424+_index*16+8(r3) @\
507-
stw r0, 8(r4) @\
508-
lwz r0, 424+_index*16+12(r3)@\
509-
stw r0, 12(r4) @\
510-
lvx v ## _index,0,r4 @\
511-
Ldone ## _index:
500+
andi. %r0, %r5, (1<<(31-_index)) SEPARATOR \
501+
beq Ldone ## _index SEPARATOR \
502+
lwz %r0, 424+_index*16(%r3) SEPARATOR \
503+
stw %r0, 0(%r4) SEPARATOR \
504+
lwz %r0, 424+_index*16+4(%r3) SEPARATOR \
505+
stw %r0, 4(%r4) SEPARATOR \
506+
lwz %r0, 424+_index*16+8(%r3) SEPARATOR \
507+
stw %r0, 8(%r4) SEPARATOR \
508+
lwz %r0, 424+_index*16+12(%r3) SEPARATOR \
509+
stw %r0, 12(%r4) SEPARATOR \
510+
lvx %v ## _index, 0, %r4 SEPARATOR \
511+
Ldone ## _index:
512512

513513

514514
LOAD_VECTOR_UNALIGNEDl(0)
@@ -545,17 +545,17 @@ Ldone ## _index:
545545
LOAD_VECTOR_UNALIGNEDh(31)
546546

547547
Lnovec:
548-
lwz r0, 136(r3) ; __cr
549-
mtocrf 255,r0
550-
lwz r0, 148(r3) ; __ctr
551-
mtctr r0
552-
lwz r0, 0(r3) ; __ssr0
553-
mtctr r0
554-
lwz r0, 8(r3) ; do r0 now
555-
lwz r5,28(r3) ; do r5 now
556-
lwz r4,24(r3) ; do r4 now
557-
lwz r1,12(r3) ; do sp now
558-
lwz r3,20(r3) ; do r3 last
548+
lwz %r0, 136(%r3) // __cr
549+
mtcr %r0
550+
lwz %r0, 148(%r3) // __ctr
551+
mtctr %r0
552+
lwz %r0, 0(%r3) // __ssr0
553+
mtctr %r0
554+
lwz %r0, 8(%r3) // do r0 now
555+
lwz %r5, 28(%r3) // do r5 now
556+
lwz %r4, 24(%r3) // do r4 now
557+
lwz %r1, 12(%r3) // do sp now
558+
lwz %r3, 20(%r3) // do r3 last
559559
bctr
560560

561561
#elif defined(__arm64__) || defined(__aarch64__)

‎libunwind/src/UnwindRegistersSave.S

Lines changed: 135 additions & 135 deletions
Original file line numberDiff line numberDiff line change
@@ -557,144 +557,144 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
557557

558558
#elif defined(__ppc__)
559559

560-
;
561-
; extern int unw_getcontext(unw_context_t* thread_state)
562-
;
563-
; On entry:
564-
; thread_state pointer is in r3
565-
;
560+
//
561+
// extern int unw_getcontext(unw_context_t* thread_state)
562+
//
563+
// On entry:
564+
// thread_state pointer is in r3
565+
//
566566
DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
567-
stw r0, 8(r3)
568-
mflr r0
569-
stw r0, 0(r3) ; store lr as ssr0
570-
stw r1, 12(r3)
571-
stw r2, 16(r3)
572-
stw r3, 20(r3)
573-
stw r4, 24(r3)
574-
stw r5, 28(r3)
575-
stw r6, 32(r3)
576-
stw r7, 36(r3)
577-
stw r8, 40(r3)
578-
stw r9, 44(r3)
579-
stw r10, 48(r3)
580-
stw r11, 52(r3)
581-
stw r12, 56(r3)
582-
stw r13, 60(r3)
583-
stw r14, 64(r3)
584-
stw r15, 68(r3)
585-
stw r16, 72(r3)
586-
stw r17, 76(r3)
587-
stw r18, 80(r3)
588-
stw r19, 84(r3)
589-
stw r20, 88(r3)
590-
stw r21, 92(r3)
591-
stw r22, 96(r3)
592-
stw r23,100(r3)
593-
stw r24,104(r3)
594-
stw r25,108(r3)
595-
stw r26,112(r3)
596-
stw r27,116(r3)
597-
stw r28,120(r3)
598-
stw r29,124(r3)
599-
stw r30,128(r3)
600-
stw r31,132(r3)
601-
602-
; save VRSave register
603-
mfspr r0,256
604-
stw r0,156(r3)
605-
; save CR registers
606-
mfcr r0
607-
stw r0,136(r3)
608-
; save CTR register
609-
mfctr r0
610-
stw r0,148(r3)
611-
612-
; save float registers
613-
stfd f0, 160(r3)
614-
stfd f1, 168(r3)
615-
stfd f2, 176(r3)
616-
stfd f3, 184(r3)
617-
stfd f4, 192(r3)
618-
stfd f5, 200(r3)
619-
stfd f6, 208(r3)
620-
stfd f7, 216(r3)
621-
stfd f8, 224(r3)
622-
stfd f9, 232(r3)
623-
stfd f10,240(r3)
624-
stfd f11,248(r3)
625-
stfd f12,256(r3)
626-
stfd f13,264(r3)
627-
stfd f14,272(r3)
628-
stfd f15,280(r3)
629-
stfd f16,288(r3)
630-
stfd f17,296(r3)
631-
stfd f18,304(r3)
632-
stfd f19,312(r3)
633-
stfd f20,320(r3)
634-
stfd f21,328(r3)
635-
stfd f22,336(r3)
636-
stfd f23,344(r3)
637-
stfd f24,352(r3)
638-
stfd f25,360(r3)
639-
stfd f26,368(r3)
640-
stfd f27,376(r3)
641-
stfd f28,384(r3)
642-
stfd f29,392(r3)
643-
stfd f30,400(r3)
644-
stfd f31,408(r3)
645-
646-
647-
; save vector registers
648-
649-
subi r4,r1,16
650-
rlwinm r4,r4,0,0,27 ; mask low 4-bits
651-
; r4 is now a 16-byte aligned pointer into the red zone
567+
stw %r0, 8(%r3)
568+
mflr %r0
569+
stw %r0, 0(%r3) // store lr as ssr0
570+
stw %r1, 12(%r3)
571+
stw %r2, 16(%r3)
572+
stw %r3, 20(%r3)
573+
stw %r4, 24(%r3)
574+
stw %r5, 28(%r3)
575+
stw %r6, 32(%r3)
576+
stw %r7, 36(%r3)
577+
stw %r8, 40(%r3)
578+
stw %r9, 44(%r3)
579+
stw %r10, 48(%r3)
580+
stw %r11, 52(%r3)
581+
stw %r12, 56(%r3)
582+
stw %r13, 60(%r3)
583+
stw %r14, 64(%r3)
584+
stw %r15, 68(%r3)
585+
stw %r16, 72(%r3)
586+
stw %r17, 76(%r3)
587+
stw %r18, 80(%r3)
588+
stw %r19, 84(%r3)
589+
stw %r20, 88(%r3)
590+
stw %r21, 92(%r3)
591+
stw %r22, 96(%r3)
592+
stw %r23,100(%r3)
593+
stw %r24,104(%r3)
594+
stw %r25,108(%r3)
595+
stw %r26,112(%r3)
596+
stw %r27,116(%r3)
597+
stw %r28,120(%r3)
598+
stw %r29,124(%r3)
599+
stw %r30,128(%r3)
600+
stw %r31,132(%r3)
601+
602+
// save VRSave register
603+
mfspr %r0, 256
604+
stw %r0, 156(%r3)
605+
// save CR registers
606+
mfcr %r0
607+
stw %r0, 136(%r3)
608+
// save CTR register
609+
mfctr %r0
610+
stw %r0, 148(%r3)
611+
612+
// save float registers
613+
stfd %f0, 160(%r3)
614+
stfd %f1, 168(%r3)
615+
stfd %f2, 176(%r3)
616+
stfd %f3, 184(%r3)
617+
stfd %f4, 192(%r3)
618+
stfd %f5, 200(%r3)
619+
stfd %f6, 208(%r3)
620+
stfd %f7, 216(%r3)
621+
stfd %f8, 224(%r3)
622+
stfd %f9, 232(%r3)
623+
stfd %f10,240(%r3)
624+
stfd %f11,248(%r3)
625+
stfd %f12,256(%r3)
626+
stfd %f13,264(%r3)
627+
stfd %f14,272(%r3)
628+
stfd %f15,280(%r3)
629+
stfd %f16,288(%r3)
630+
stfd %f17,296(%r3)
631+
stfd %f18,304(%r3)
632+
stfd %f19,312(%r3)
633+
stfd %f20,320(%r3)
634+
stfd %f21,328(%r3)
635+
stfd %f22,336(%r3)
636+
stfd %f23,344(%r3)
637+
stfd %f24,352(%r3)
638+
stfd %f25,360(%r3)
639+
stfd %f26,368(%r3)
640+
stfd %f27,376(%r3)
641+
stfd %f28,384(%r3)
642+
stfd %f29,392(%r3)
643+
stfd %f30,400(%r3)
644+
stfd %f31,408(%r3)
645+
646+
647+
// save vector registers
648+
649+
subi %r4, %r1, 16
650+
rlwinm %r4, %r4, 0, 0, 27 // mask low 4-bits
651+
// r4 is now a 16-byte aligned pointer into the red zone
652652

653653
#define SAVE_VECTOR_UNALIGNED(_vec, _offset) \
654-
stvx _vec,0,r4 @\
655-
lwz r5, 0(r4) @\
656-
stw r5, _offset(r3) @\
657-
lwz r5, 4(r4) @\
658-
stw r5, _offset+4(r3) @\
659-
lwz r5, 8(r4) @\
660-
stw r5, _offset+8(r3) @\
661-
lwz r5, 12(r4) @\
662-
stw r5, _offset+12(r3)
663-
664-
SAVE_VECTOR_UNALIGNED( v0, 424+0x000)
665-
SAVE_VECTOR_UNALIGNED( v1, 424+0x010)
666-
SAVE_VECTOR_UNALIGNED( v2, 424+0x020)
667-
SAVE_VECTOR_UNALIGNED( v3, 424+0x030)
668-
SAVE_VECTOR_UNALIGNED( v4, 424+0x040)
669-
SAVE_VECTOR_UNALIGNED( v5, 424+0x050)
670-
SAVE_VECTOR_UNALIGNED( v6, 424+0x060)
671-
SAVE_VECTOR_UNALIGNED( v7, 424+0x070)
672-
SAVE_VECTOR_UNALIGNED( v8, 424+0x080)
673-
SAVE_VECTOR_UNALIGNED( v9, 424+0x090)
674-
SAVE_VECTOR_UNALIGNED(v10, 424+0x0A0)
675-
SAVE_VECTOR_UNALIGNED(v11, 424+0x0B0)
676-
SAVE_VECTOR_UNALIGNED(v12, 424+0x0C0)
677-
SAVE_VECTOR_UNALIGNED(v13, 424+0x0D0)
678-
SAVE_VECTOR_UNALIGNED(v14, 424+0x0E0)
679-
SAVE_VECTOR_UNALIGNED(v15, 424+0x0F0)
680-
SAVE_VECTOR_UNALIGNED(v16, 424+0x100)
681-
SAVE_VECTOR_UNALIGNED(v17, 424+0x110)
682-
SAVE_VECTOR_UNALIGNED(v18, 424+0x120)
683-
SAVE_VECTOR_UNALIGNED(v19, 424+0x130)
684-
SAVE_VECTOR_UNALIGNED(v20, 424+0x140)
685-
SAVE_VECTOR_UNALIGNED(v21, 424+0x150)
686-
SAVE_VECTOR_UNALIGNED(v22, 424+0x160)
687-
SAVE_VECTOR_UNALIGNED(v23, 424+0x170)
688-
SAVE_VECTOR_UNALIGNED(v24, 424+0x180)
689-
SAVE_VECTOR_UNALIGNED(v25, 424+0x190)
690-
SAVE_VECTOR_UNALIGNED(v26, 424+0x1A0)
691-
SAVE_VECTOR_UNALIGNED(v27, 424+0x1B0)
692-
SAVE_VECTOR_UNALIGNED(v28, 424+0x1C0)
693-
SAVE_VECTOR_UNALIGNED(v29, 424+0x1D0)
694-
SAVE_VECTOR_UNALIGNED(v30, 424+0x1E0)
695-
SAVE_VECTOR_UNALIGNED(v31, 424+0x1F0)
696-
697-
li r3, 0 ; return UNW_ESUCCESS
654+
stvx _vec, 0, %r4 SEPARATOR \
655+
lwz %r5, 0(%r4) SEPARATOR \
656+
stw %r5, _offset(%r3) SEPARATOR \
657+
lwz %r5, 4(%r4) SEPARATOR \
658+
stw %r5, _offset+4(%r3) SEPARATOR \
659+
lwz %r5, 8(%r4) SEPARATOR \
660+
stw %r5, _offset+8(%r3) SEPARATOR \
661+
lwz %r5, 12(%r4) SEPARATOR \
662+
stw %r5, _offset+12(%r3)
663+
664+
SAVE_VECTOR_UNALIGNED( %v0, 424+0x000)
665+
SAVE_VECTOR_UNALIGNED( %v1, 424+0x010)
666+
SAVE_VECTOR_UNALIGNED( %v2, 424+0x020)
667+
SAVE_VECTOR_UNALIGNED( %v3, 424+0x030)
668+
SAVE_VECTOR_UNALIGNED( %v4, 424+0x040)
669+
SAVE_VECTOR_UNALIGNED( %v5, 424+0x050)
670+
SAVE_VECTOR_UNALIGNED( %v6, 424+0x060)
671+
SAVE_VECTOR_UNALIGNED( %v7, 424+0x070)
672+
SAVE_VECTOR_UNALIGNED( %v8, 424+0x080)
673+
SAVE_VECTOR_UNALIGNED( %v9, 424+0x090)
674+
SAVE_VECTOR_UNALIGNED(%v10, 424+0x0A0)
675+
SAVE_VECTOR_UNALIGNED(%v11, 424+0x0B0)
676+
SAVE_VECTOR_UNALIGNED(%v12, 424+0x0C0)
677+
SAVE_VECTOR_UNALIGNED(%v13, 424+0x0D0)
678+
SAVE_VECTOR_UNALIGNED(%v14, 424+0x0E0)
679+
SAVE_VECTOR_UNALIGNED(%v15, 424+0x0F0)
680+
SAVE_VECTOR_UNALIGNED(%v16, 424+0x100)
681+
SAVE_VECTOR_UNALIGNED(%v17, 424+0x110)
682+
SAVE_VECTOR_UNALIGNED(%v18, 424+0x120)
683+
SAVE_VECTOR_UNALIGNED(%v19, 424+0x130)
684+
SAVE_VECTOR_UNALIGNED(%v20, 424+0x140)
685+
SAVE_VECTOR_UNALIGNED(%v21, 424+0x150)
686+
SAVE_VECTOR_UNALIGNED(%v22, 424+0x160)
687+
SAVE_VECTOR_UNALIGNED(%v23, 424+0x170)
688+
SAVE_VECTOR_UNALIGNED(%v24, 424+0x180)
689+
SAVE_VECTOR_UNALIGNED(%v25, 424+0x190)
690+
SAVE_VECTOR_UNALIGNED(%v26, 424+0x1A0)
691+
SAVE_VECTOR_UNALIGNED(%v27, 424+0x1B0)
692+
SAVE_VECTOR_UNALIGNED(%v28, 424+0x1C0)
693+
SAVE_VECTOR_UNALIGNED(%v29, 424+0x1D0)
694+
SAVE_VECTOR_UNALIGNED(%v30, 424+0x1E0)
695+
SAVE_VECTOR_UNALIGNED(%v31, 424+0x1F0)
696+
697+
li %r3, 0 // return UNW_ESUCCESS
698698
blr
699699

700700

‎libunwind/src/assembly.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,6 @@
2929
#ifdef _ARCH_PWR8
3030
#define PPC64_HAS_VMX
3131
#endif
32-
#elif defined(__POWERPC__) || defined(__powerpc__) || defined(__ppc__)
33-
#define SEPARATOR @
3432
#elif defined(__arm64__)
3533
#define SEPARATOR %%
3634
#else

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