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[AMDGPU][AsmParser] Refine parsing SDWA operands.
Removes the need for the custom code in parseCustomOperand(). Reviewed By: foad Differential Revision: https://reviews.llvm.org/D147241
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+37
-34
lines changed

2 files changed

+37
-34
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 22 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -126,10 +126,10 @@ class AMDGPUOperand : public MCParsedAsmOperand {
126126
ImmTyD16,
127127
ImmTyClampSI,
128128
ImmTyOModSI,
129-
ImmTySdwaDstSel,
130-
ImmTySdwaSrc0Sel,
131-
ImmTySdwaSrc1Sel,
132-
ImmTySdwaDstUnused,
129+
ImmTySDWADstSel,
130+
ImmTySDWASrc0Sel,
131+
ImmTySDWASrc1Sel,
132+
ImmTySDWADstUnused,
133133
ImmTyDMask,
134134
ImmTyDim,
135135
ImmTyUNorm,
@@ -386,10 +386,10 @@ class AMDGPUOperand : public MCParsedAsmOperand {
386386
bool isRowMask() const { return isImmTy(ImmTyDppRowMask); }
387387
bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }
388388
bool isFI() const { return isImmTy(ImmTyDppFi); }
389-
bool isSDWADstSel() const { return isImmTy(ImmTySdwaDstSel); }
390-
bool isSDWASrc0Sel() const { return isImmTy(ImmTySdwaSrc0Sel); }
391-
bool isSDWASrc1Sel() const { return isImmTy(ImmTySdwaSrc1Sel); }
392-
bool isSDWADstUnused() const { return isImmTy(ImmTySdwaDstUnused); }
389+
bool isSDWADstSel() const { return isImmTy(ImmTySDWADstSel); }
390+
bool isSDWASrc0Sel() const { return isImmTy(ImmTySDWASrc0Sel); }
391+
bool isSDWASrc1Sel() const { return isImmTy(ImmTySDWASrc1Sel); }
392+
bool isSDWADstUnused() const { return isImmTy(ImmTySDWADstUnused); }
393393
bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }
394394
bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }
395395
bool isAttrChan() const { return isImmTy(ImmTyAttrChan); }
@@ -1049,10 +1049,10 @@ class AMDGPUOperand : public MCParsedAsmOperand {
10491049
case ImmTyDppBankMask: OS << "DppBankMask"; break;
10501050
case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break;
10511051
case ImmTyDppFi: OS << "FI"; break;
1052-
case ImmTySdwaDstSel: OS << "SdwaDstSel"; break;
1053-
case ImmTySdwaSrc0Sel: OS << "SdwaSrc0Sel"; break;
1054-
case ImmTySdwaSrc1Sel: OS << "SdwaSrc1Sel"; break;
1055-
case ImmTySdwaDstUnused: OS << "SdwaDstUnused"; break;
1052+
case ImmTySDWADstSel: OS << "SDWADstSel"; break;
1053+
case ImmTySDWASrc0Sel: OS << "SDWASrc0Sel"; break;
1054+
case ImmTySDWASrc1Sel: OS << "SDWASrc1Sel"; break;
1055+
case ImmTySDWADstUnused: OS << "SDWADstUnused"; break;
10561056
case ImmTyDMask: OS << "DMask"; break;
10571057
case ImmTyDim: OS << "Dim"; break;
10581058
case ImmTyUNorm: OS << "UNorm"; break;
@@ -8939,7 +8939,7 @@ AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
89398939
return MatchOperand_ParseFail;
89408940
}
89418941

8942-
Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySdwaDstUnused));
8942+
Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySDWADstUnused));
89438943
return MatchOperand_Success;
89448944
}
89458945

@@ -9026,14 +9026,14 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
90269026

90279027
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel))
90289028
addOptionalImmOperand(Inst, Operands, OptionalIdx,
9029-
AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);
9029+
AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);
90309030

90319031
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused))
90329032
addOptionalImmOperand(Inst, Operands, OptionalIdx,
9033-
AMDGPUOperand::ImmTySdwaDstUnused,
9033+
AMDGPUOperand::ImmTySDWADstUnused,
90349034
DstUnused::UNUSED_PRESERVE);
90359035

9036-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
9036+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
90379037
break;
90389038

90399039
case SIInstrFlags::VOP2:
@@ -9042,17 +9042,17 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
90429042
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod))
90439043
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);
90449044

9045-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);
9046-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::UNUSED_PRESERVE);
9047-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
9048-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD);
9045+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);
9046+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE);
9047+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
9048+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);
90499049
break;
90509050

90519051
case SIInstrFlags::VOPC:
90529052
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp))
90539053
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
9054-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
9055-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD);
9054+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
9055+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);
90569056
break;
90579057

90589058
default:
@@ -9155,14 +9155,6 @@ AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) {
91559155
case MCK_ImmRowMask:
91569156
return parseIntWithPrefix("row_mask", Operands,
91579157
AMDGPUOperand::ImmTyDppRowMask);
9158-
case MCK_ImmSDWADstSel:
9159-
return parseSDWASel(Operands, "dst_sel", AMDGPUOperand::ImmTySdwaDstSel);
9160-
case MCK_ImmSDWADstUnused:
9161-
return parseSDWADstUnused(Operands);
9162-
case MCK_ImmSDWASrc0Sel:
9163-
return parseSDWASel(Operands, "src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel);
9164-
case MCK_ImmSDWASrc1Sel:
9165-
return parseSDWASel(Operands, "src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel);
91669158
case MCK_tfe:
91679159
return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);
91689160
}

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1207,6 +1207,17 @@ class NamedOperandU32Default1<string Name, AsmOperandClass MatchClass> :
12071207
let ParserMatchClass = MatchClass;
12081208
}
12091209

1210+
class SDWAOperandClass<string Id, string Name>
1211+
: CustomOperandClass<Name, 1> {
1212+
string ImmTy = "AMDGPUOperand::ImmTy"#Name;
1213+
let ParserMethod =
1214+
"[this](OperandVector &Operands) -> OperandMatchResultTy { "#
1215+
"return parseSDWASel(Operands, \""#Id#"\", "#ImmTy#"); }";
1216+
}
1217+
1218+
class SDWAOperand<string Id, string Name = NAME>
1219+
: CustomOperand<i32, 1, Name, SDWAOperandClass<Id, Name>>;
1220+
12101221
let OperandType = "OPERAND_IMMEDIATE" in {
12111222

12121223
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
@@ -1247,10 +1258,10 @@ def FORMAT : CustomOperand<i8>;
12471258
def DMask : NamedIntOperand<i16, "dmask">;
12481259
def Dim : CustomOperand<i8>;
12491260

1250-
def dst_sel : NamedOperandU32<"SDWADstSel", NamedMatchClass<"SDWADstSel">>;
1251-
def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>;
1252-
def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
1253-
def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>;
1261+
def dst_sel : SDWAOperand<"dst_sel", "SDWADstSel">;
1262+
def src0_sel : SDWAOperand<"src0_sel", "SDWASrc0Sel">;
1263+
def src1_sel : SDWAOperand<"src1_sel", "SDWASrc1Sel">;
1264+
def dst_unused : CustomOperand<i32, 1, "SDWADstUnused">;
12541265

12551266
def op_sel0 : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>;
12561267
def op_sel_hi0 : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>;

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