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[AMDGPU][AsmParser][NFCI] All NamedIntOperands to be of the i32 type. (#102616)
There's no need for them to have different types. Part of <#62629>.
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llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 18 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1017,9 +1017,8 @@ def SDWAVopcDst : BoolRC {
10171017
let PrintMethod = "printVOPDst";
10181018
}
10191019

1020-
class NamedIntOperand<ValueType Type, string prefix, bit Optional = 1,
1021-
string name = NAME>
1022-
: CustomOperand<Type, Optional, name> {
1020+
class NamedIntOperand<string prefix, bit Optional = 1, string name = NAME>
1021+
: CustomOperand<i32, Optional, name> {
10231022
string Prefix = prefix;
10241023

10251024
let PredicateMethod =
@@ -1079,10 +1078,10 @@ class ArrayOperand0<string Id, string Name = NAME>
10791078
let ImmTy = "ImmTyOffset" in
10801079
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
10811080
let PrintMethod = "printOffset" in
1082-
def Offset : NamedIntOperand<i32, "offset">;
1081+
def Offset : NamedIntOperand<"offset">;
10831082
let Validator = "isUInt<8>" in {
1084-
def Offset0 : NamedIntOperand<i32, "offset0">;
1085-
def Offset1 : NamedIntOperand<i32, "offset1">;
1083+
def Offset0 : NamedIntOperand<"offset0">;
1084+
def Offset1 : NamedIntOperand<"offset1">;
10861085
}
10871086

10881087
def gds : NamedBitOperand<"gds", "GDS">;
@@ -1118,7 +1117,7 @@ def exp_vm : NamedBitOperand<"vm", "ExpVM">;
11181117
def FORMAT : CustomOperand<i8>;
11191118

11201119
let PrintInHex = 1 in
1121-
def DMask : NamedIntOperand<i16, "dmask">;
1120+
def DMask : NamedIntOperand<"dmask">;
11221121

11231122
def Dim : CustomOperand<i8, /*optional=*/1>;
11241123

@@ -1139,46 +1138,46 @@ def dpp8 : CustomOperand<i32, 0, "DPP8">;
11391138
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;
11401139

11411140
let DefaultValue = "0xf", PrintInHex = 1, AlwaysPrint = 1 in {
1142-
def DppRowMask : NamedIntOperand<i32, "row_mask">;
1143-
def DppBankMask : NamedIntOperand<i32, "bank_mask">;
1141+
def DppRowMask : NamedIntOperand<"row_mask">;
1142+
def DppBankMask : NamedIntOperand<"bank_mask">;
11441143
}
1145-
def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl"> {
1144+
def DppBoundCtrl : NamedIntOperand<"bound_ctrl"> {
11461145
let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }";
11471146
let PrintMethod = "printDppBoundCtrl";
11481147
}
11491148

11501149
let DecoderMethod = "decodeDpp8FI", PrintMethod = "printDppFI" in
1151-
def Dpp8FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
1150+
def Dpp8FI : NamedIntOperand<"fi", 1, "DppFI">;
11521151
let PrintMethod = "printDppFI" in
1153-
def Dpp16FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
1152+
def Dpp16FI : NamedIntOperand<"fi", 1, "DppFI">;
11541153

11551154
def blgp : CustomOperand<i32, 1, "BLGP">;
1156-
def CBSZ : NamedIntOperand<i32, "cbsz"> {
1155+
def CBSZ : NamedIntOperand<"cbsz"> {
11571156
let Validator = "isUInt<3>";
11581157
}
1159-
def ABID : NamedIntOperand<i32, "abid"> {
1158+
def ABID : NamedIntOperand<"abid"> {
11601159
let Validator = "isUInt<4>";
11611160
}
11621161
def hwreg : CustomOperand<i32, 0, "Hwreg">;
11631162

11641163
def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
11651164

11661165
let AlwaysPrint = 1 in {
1167-
def WaitVDST : NamedIntOperand<i8, "wait_vdst"> {
1166+
def WaitVDST : NamedIntOperand<"wait_vdst"> {
11681167
let Validator = "isUInt<4>";
11691168
}
1170-
def WaitEXP : NamedIntOperand<i8, "wait_exp"> {
1169+
def WaitEXP : NamedIntOperand<"wait_exp"> {
11711170
let Validator = "isUInt<3>";
11721171
}
1173-
def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst"> {
1172+
def WaitVAVDst : NamedIntOperand<"wait_va_vdst"> {
11741173
let Validator = "isUInt<4>";
11751174
}
1176-
def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc"> {
1175+
def WaitVMVSrc : NamedIntOperand<"wait_vm_vsrc"> {
11771176
let Validator = "isUInt<1>";
11781177
}
11791178
} // End AlwaysPrint = 1
11801179

1181-
def ByteSel : NamedIntOperand<i8, "byte_sel"> {
1180+
def ByteSel : NamedIntOperand<"byte_sel"> {
11821181
let Validator = "isUInt<2>";
11831182
}
11841183

llvm/lib/Target/AMDGPU/SMInstructions.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,11 @@ def smrd_offset_8 : ImmOperand<i32, "SMRDOffset8", 1>;
1111
let EncoderMethod = "getSMEMOffsetEncoding",
1212
DecoderMethod = "decodeSMEMOffset" in {
1313
def SMEMOffset : ImmOperand<i32, "SMEMOffset", 1>;
14-
def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0> {
14+
def SMEMOffsetMod : NamedIntOperand<"offset", 0> {
1515
let AlwaysPrint = 1;
1616
let PrintInHex = 1;
1717
}
18-
def OptSMEMOffsetMod : NamedIntOperand<i32, "offset"> {
18+
def OptSMEMOffsetMod : NamedIntOperand<"offset"> {
1919
let ImmTy = SMEMOffsetMod.ImmTy;
2020
let PredicateMethod = SMEMOffsetMod.PredicateMethod;
2121
let PrintMethod = SMEMOffsetMod.PrintMethod;

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