Replace 0-31 with !range to align others

wangpc-pp · wangpc-pp · commit 33dec911d7e7 · 2023-09-27T12:09:39.000+08:00
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -416,7 +416,7 @@ class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> {
 }
 
 // Vector registers
-foreach Index = 0-31 in {
+foreach Index = !range(0, 32, 1) in {
   def V#Index : RISCVReg<Index, "v"#Index>, DwarfRegNum<[!add(Index, 96)]>;
 }
 

Original file line number	Diff line number	Diff line change
`@@ -416,7 +416,7 @@ class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> {`
`416`	`416`	`}`
`417`	`417`
`418`	`418`	`// Vector registers`
`419`		`-foreach Index = 0-31 in {`
	`419`	`+foreach Index = !range(0, 32, 1) in {`
`420`	`420`	`def V#Index : RISCVReg<Index, "v"#Index>, DwarfRegNum<[!add(Index, 96)]>;`
`421`	`421`	`}`
`422`	`422`