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1 parent e13e848 commit 36306fdCopy full SHA for 36306fd
llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1622,7 +1622,8 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
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report("G_VSCALE immediate cannot be zero", MI);
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break;
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}
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-
+ break;
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+ }
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case TargetOpcode::G_INSERT_SUBVECTOR: {
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const MachineOperand &Src0Op = MI->getOperand(1);
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if (!Src0Op.isReg()) {
llvm/test/MachineVerifier/test_g_vscale.mir
@@ -5,11 +5,11 @@ name: g_vscale
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body: |
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bb.0:
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- %1:_(s32) = G_CONSTANT 4
+ %1:_(s32) = G_CONSTANT i32 4
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; CHECK: G_VSCALE operand must be cimm
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%2:_(s32) = G_VSCALE %1
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; CHECK: G_VSCALE immediate cannot be zero
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- %3:_(s32) = G_VSCALE 0
+ %3:_(s32) = G_VSCALE i32 0
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...
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