Skip to content

Commit 3912ef0

Browse files
Rot127Rot127
committed
Add writeback information to STC and LDC instructions.
1 parent 3353f7d commit 3912ef0

File tree

4 files changed

+27
-18
lines changed

4 files changed

+27
-18
lines changed

‎llvm/lib/Target/ARM/ARMInstrFormats.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1390,8 +1390,8 @@ class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
13901390
}
13911391

13921392
class T2I<dag oops, dag iops, InstrItinClass itin,
1393-
string opc, string asm, list<dag> pattern, AddrMode am = AddrModeNone>
1394-
: Thumb2I<oops, iops, am, 4, itin, opc, asm, "", pattern>;
1393+
string opc, string asm, list<dag> pattern, AddrMode am = AddrModeNone, string constraints = "">
1394+
: Thumb2I<oops, iops, am, 4, itin, opc, asm, constraints, pattern>;
13951395
class T2Ii12<dag oops, dag iops, InstrItinClass itin,
13961396
string opc, string asm, list<dag> pattern>
13971397
: Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;

‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5440,25 +5440,25 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
54405440
}
54415441

54425442
class ACI<dag oops, dag iops, string opc, string asm,
5443-
list<dag> pattern, IndexMode im = IndexModeNone,
5443+
list<dag> pattern, string cstrs = "", IndexMode im = IndexModeNone,
54445444
AddrMode am = AddrModeNone>
54455445
: I<oops, iops, am, 4, im, BrFrm, NoItinerary,
5446-
opc, asm, "", pattern> {
5446+
opc, asm, cstrs, pattern> {
54475447
let Inst{27-25} = 0b110;
54485448
}
54495449
class ACInoP<dag oops, dag iops, string opc, string asm,
5450-
list<dag> pattern, IndexMode im = IndexModeNone,
5450+
list<dag> pattern, string constraints = "", IndexMode im = IndexModeNone,
54515451
AddrMode am = AddrModeNone>
54525452
: InoP<oops, iops, am, 4, im, BrFrm, NoItinerary,
5453-
opc, asm, "", pattern> {
5453+
opc, asm, constraints, pattern> {
54545454
let Inst{31-28} = 0b1111;
54555455
let Inst{27-25} = 0b110;
54565456
}
54575457

54585458
let DecoderNamespace = "CoProc" in {
54595459
multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
54605460
def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
5461-
asm, "\t$cop, $CRd, $addr", pattern, IndexModeNone,
5461+
asm, "\t$cop, $CRd, $addr", pattern, "", IndexModeNone,
54625462
AddrMode5> {
54635463
bits<13> addr;
54645464
bits<4> cop;
@@ -5474,8 +5474,8 @@ multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
54745474
let Inst{7-0} = addr{7-0};
54755475
let DecoderMethod = "DecodeCopMemInstruction";
54765476
}
5477-
def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5478-
asm, "\t$cop, $CRd, $addr!", [], IndexModePre> {
5477+
def _PRE : ACI<(outs GPR:$Rn_wb), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5478+
asm, "\t$cop, $CRd, $addr!", [], "$addr.base = $Rn_wb", IndexModePre> {
54795479
bits<13> addr;
54805480
bits<4> cop;
54815481
bits<4> CRd;
@@ -5492,7 +5492,7 @@ multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
54925492
}
54935493
def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
54945494
postidx_imm8s4:$offset),
5495-
asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> {
5495+
asm, "\t$cop, $CRd, $addr, $offset", [], "", IndexModePost> {
54965496
bits<9> offset;
54975497
bits<4> addr;
54985498
bits<4> cop;
@@ -5530,7 +5530,7 @@ multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
55305530
}
55315531
multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
55325532
def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
5533-
asm, "\t$cop, $CRd, $addr", pattern, IndexModeNone,
5533+
asm, "\t$cop, $CRd, $addr", pattern, "", IndexModeNone,
55345534
AddrMode5> {
55355535
bits<13> addr;
55365536
bits<4> cop;
@@ -5546,8 +5546,8 @@ multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
55465546
let Inst{7-0} = addr{7-0};
55475547
let DecoderMethod = "DecodeCopMemInstruction";
55485548
}
5549-
def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5550-
asm, "\t$cop, $CRd, $addr!", [], IndexModePre> {
5549+
def _PRE : ACInoP<(outs GPR:$Rn_wb), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5550+
asm, "\t$cop, $CRd, $addr!", [], "$addr.base = $Rn_wb", IndexModePre> {
55515551
bits<13> addr;
55525552
bits<4> cop;
55535553
bits<4> CRd;
@@ -5564,7 +5564,7 @@ multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
55645564
}
55655565
def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
55665566
postidx_imm8s4:$offset),
5567-
asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> {
5567+
asm, "\t$cop, $CRd, $addr, $offset", [], "", IndexModePost> {
55685568
bits<9> offset;
55695569
bits<4> addr;
55705570
bits<4> cop;

‎llvm/lib/Target/ARM/ARMInstrThumb2.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4383,8 +4383,8 @@ def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
43834383
// Coprocessor load/store -- for disassembly only
43844384
//
43854385
class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm,
4386-
list<dag> pattern, AddrMode am = AddrModeNone>
4387-
: T2I<oops, iops, NoItinerary, opc, asm, pattern, am> {
4386+
list<dag> pattern, AddrMode am = AddrModeNone, string constraints = "">
4387+
: T2I<oops, iops, NoItinerary, opc, asm, pattern, am, constraints> {
43884388
let Inst{31-28} = op31_28;
43894389
let Inst{27-25} = 0b110;
43904390
}
@@ -4408,8 +4408,8 @@ multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag>
44084408
let DecoderMethod = "DecodeCopMemInstruction";
44094409
}
44104410
def _PRE : T2CI<op31_28,
4411-
(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4412-
asm, "\t$cop, $CRd, $addr!", []> {
4411+
(outs GPR:$Rn_wb), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4412+
asm, "\t$cop, $CRd, $addr!", [], AddrMode5, "$addr.base = $Rn_wb"> {
44134413
bits<13> addr;
44144414
bits<4> cop;
44154415
bits<4> CRd;

‎llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1862,12 +1862,17 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
18621862
const MCDisassembler *Decoder) {
18631863
DecodeStatus S = MCDisassembler::Success;
18641864

1865+
unsigned P = fieldFromInstruction(Insn, 24, 1);
1866+
unsigned W = fieldFromInstruction(Insn, 21, 1);
18651867
unsigned pred = fieldFromInstruction(Insn, 28, 4);
18661868
unsigned CRd = fieldFromInstruction(Insn, 12, 4);
18671869
unsigned coproc = fieldFromInstruction(Insn, 8, 4);
18681870
unsigned imm = fieldFromInstruction(Insn, 0, 8);
18691871
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
18701872
unsigned U = fieldFromInstruction(Insn, 23, 1);
1873+
// Pre-Indexed implies writeback to Rn
1874+
bool IsPreIndexed = (P == 1) && (W == 1);
1875+
18711876
const FeatureBitset &featureBits =
18721877
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
18731878

@@ -1943,6 +1948,10 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
19431948
if (featureBits[ARM::HasV8Ops] && (coproc != 14))
19441949
return MCDisassembler::Fail;
19451950

1951+
if (IsPreIndexed)
1952+
// Dummy operand for Rn_wb.
1953+
Inst.addOperand(MCOperand::createImm(0));
1954+
19461955
Inst.addOperand(MCOperand::createImm(coproc));
19471956
Inst.addOperand(MCOperand::createImm(CRd));
19481957
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))

0 commit comments

Comments
 (0)