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V-FEXrtV-FEXrt
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cleanup
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4 files changed

+18
-21
lines changed

4 files changed

+18
-21
lines changed

‎llvm/include/llvm/IR/IntrinsicsDirectX.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,5 @@ def int_dx_splitdouble : DefaultAttrsIntrinsic<[llvm_anyint_ty, LLVMMatchType<0>
103103
def int_dx_radians : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
104104
def int_dx_firstbituhigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>;
105105
def int_dx_firstbitshigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>;
106-
// TODO: check this against the spec
107106
def int_dx_firstbitlow : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>;
108107
}

‎llvm/lib/Target/DirectX/DXIL.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -573,7 +573,6 @@ def FirstbitLo : DXILOp<32, unaryBits> {
573573
let overloads =
574574
[Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
575575
let stages = [Stages<DXIL1_0, [all_stages]>];
576-
// TODO: check these
577576
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
578577
}
579578

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2799,7 +2799,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
27992799
case Intrinsic::spv_firstbitshigh: // There is no CL equivalent of FindSMsb
28002800
return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/true);
28012801
case Intrinsic::spv_firstbitlow: // There is no CL equivlent of FindILsb
2802-
// (true?)
28032802
return selectFirstBitLow(ResVReg, ResType, I);
28042803
case Intrinsic::spv_group_memory_barrier_with_group_sync: {
28052804
bool Result = true;
@@ -3248,7 +3247,7 @@ bool SPIRVInstructionSelector::selectFirstBitLow64(Register ResVReg,
32483247
// Per the spec, repeat the vector if only one vec is needed
32493248
.addUse(FBLReg);
32503249

3251-
// high bits are store in even indexes. Extract them from FBLReg
3250+
// high bits are stored in even indexes. Extract them from FBLReg
32523251
for (unsigned j = 0; j < ComponentCount * 2; j += 2) {
32533252
MIB.addImm(j);
32543253
}
@@ -3262,14 +3261,14 @@ bool SPIRVInstructionSelector::selectFirstBitLow64(Register ResVReg,
32623261
// Per the spec, repeat the vector if only one vec is needed
32633262
.addUse(FBLReg);
32643263

3265-
// low bits are store in odd indexes. Extract them from FBLReg
3264+
// low bits are stored in odd indexes. Extract them from FBLReg
32663265
for (unsigned j = 1; j < ComponentCount * 2; j += 2) {
32673266
MIB.addImm(j);
32683267
}
32693268
Result = Result && MIB.constrainAllUses(TII, TRI, RBI);
32703269
}
32713270

3272-
// 4. Check if result of each bottom 32 bits is == -1
3271+
// 4. Check the result. When low bits == -1 use high, otherwise use low
32733272
SPIRVType *BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
32743273
Register NegOneReg;
32753274
Register Reg0;
@@ -3295,7 +3294,7 @@ bool SPIRVInstructionSelector::selectFirstBitLow64(Register ResVReg,
32953294
AddOp = SPIRV::OpIAddV;
32963295
}
32973296

3298-
// Check if the low bits are == -1; true if -1
3297+
// Check if the low bits are == -1
32993298
Register BReg = MRI->createVirtualRegister(GR.getRegClass(BoolType));
33003299
Result = Result && selectNAryOpWithSrcs(BReg, BoolType, I,
33013300
{LowReg, NegOneReg}, SPIRV::OpIEqual);
@@ -3305,7 +3304,7 @@ bool SPIRVInstructionSelector::selectFirstBitLow64(Register ResVReg,
33053304
Result = Result && selectNAryOpWithSrcs(TmpReg, ResType, I,
33063305
{BReg, HighReg, LowReg}, SelectOp);
33073306

3308-
// Add 32 for high bits, 0 for low bits
3307+
// 5. Add 32 when high bits are used, otherwise 0 for low bits
33093308
Register ValReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
33103309
Result = Result && selectNAryOpWithSrcs(ValReg, ResType, I,
33113310
{BReg, Reg32, Reg0}, SelectOp);

‎llvm/test/CodeGen/SPIRV/hlsl-intrinsics/firstbitlow.ll

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,13 @@
66
; CHECK-DAG: [[u32_t:%.+]] = OpTypeInt 32 0
77
; CHECK-DAG: [[u32x2_t:%.+]] = OpTypeVector [[u32_t]] 2
88
; CHECK-DAG: [[u32x4_t:%.+]] = OpTypeVector [[u32_t]] 4
9-
; CHECK-DAG: [[const_zero:%.*]] = OpConstant [[u32_t]] 0
10-
; CHECK-DAG: [[const_zerox2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_zero]] [[const_zero]]
11-
; CHECK-DAG: [[const_one:%.*]] = OpConstant [[u32_t]] 1
12-
; CHECK-DAG: [[const_thirty_two:%.*]] = OpConstant [[u32_t]] 32
13-
; CHECK-DAG: [[const_thirty_twox2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_thirty_two]] [[const_thirty_two]]
14-
; CHECK-DAG: [[const_neg_one:%.*]] = OpConstant [[u32_t]] 4294967295
15-
; CHECK-DAG: [[const_neg_onex2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_neg_one]] [[const_neg_one]]
9+
; CHECK-DAG: [[const_0:%.*]] = OpConstant [[u32_t]] 0
10+
; CHECK-DAG: [[const_0x2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_0]] [[const_0]]
11+
; CHECK-DAG: [[const_1:%.*]] = OpConstant [[u32_t]] 1
12+
; CHECK-DAG: [[const_32:%.*]] = OpConstant [[u32_t]] 32
13+
; CHECK-DAG: [[const_32x2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_32]] [[const_32]]
14+
; CHECK-DAG: [[const_neg1:%.*]] = OpConstant [[u32_t]] 4294967295
15+
; CHECK-DAG: [[const_neg1x2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_neg1]] [[const_neg1]]
1616
; CHECK-DAG: [[u16_t:%.+]] = OpTypeInt 16 0
1717
; CHECK-DAG: [[u16x2_t:%.+]] = OpTypeVector [[u16_t]] 2
1818
; CHECK-DAG: [[u64_t:%.+]] = OpTypeInt 64 0
@@ -68,11 +68,11 @@ entry:
6868
; CHECK: [[a64:%.+]] = OpFunctionParameter [[u64_t]]
6969
; CHECK: [[a32x2:%.+]] = OpBitcast [[u32x2_t]] [[a64]]
7070
; CHECK: [[lsb_bits:%.+]] = OpExtInst [[u32x2_t]] [[glsl_450_ext]] FindILsb [[a32x2]]
71-
; CHECK: [[high_bits:%.+]] = OpVectorExtractDynamic [[u32_t]] [[lsb_bits]] [[const_zero]]
72-
; CHECK: [[low_bits:%.+]] = OpVectorExtractDynamic [[u32_t]] [[lsb_bits]] [[const_one]]
73-
; CHECK: [[should_use_high:%.+]] = OpIEqual [[bool_t]] [[low_bits]] [[const_neg_one]]
71+
; CHECK: [[high_bits:%.+]] = OpVectorExtractDynamic [[u32_t]] [[lsb_bits]] [[const_0]]
72+
; CHECK: [[low_bits:%.+]] = OpVectorExtractDynamic [[u32_t]] [[lsb_bits]] [[const_1]]
73+
; CHECK: [[should_use_high:%.+]] = OpIEqual [[bool_t]] [[low_bits]] [[const_neg1]]
7474
; CHECK: [[ans_bits:%.+]] = OpSelect [[u32_t]] [[should_use_high]] [[high_bits]] [[low_bits]]
75-
; CHECK: [[ans_offset:%.+]] = OpSelect [[u32_t]] [[should_use_high]] [[const_thirty_two]] [[const_zero]]
75+
; CHECK: [[ans_offset:%.+]] = OpSelect [[u32_t]] [[should_use_high]] [[const_32]] [[const_0]]
7676
; CHECK: [[ret:%.+]] = OpIAdd [[u32_t]] [[ans_offset]] [[ans_bits]]
7777
; CHECK: OpReturnValue [[ret]]
7878
%elt.firstbitlow = call i32 @llvm.spv.firstbitlow.i64(i64 %a)
@@ -87,9 +87,9 @@ entry:
8787
; CHECK: [[lsb_bits:%.+]] = OpExtInst [[u32x4_t]] [[glsl_450_ext]] FindILsb [[a32x4]]
8888
; CHECK: [[high_bits:%.+]] = OpVectorShuffle [[u32x2_t]] [[lsb_bits]] [[lsb_bits]] 0 2
8989
; CHECK: [[low_bits:%.+]] = OpVectorShuffle [[u32x2_t]] [[lsb_bits]] [[lsb_bits]] 1 3
90-
; CHECK: [[should_use_high:%.+]] = OpIEqual [[boolx2_t]] [[low_bits]] [[const_neg_onex2]]
90+
; CHECK: [[should_use_high:%.+]] = OpIEqual [[boolx2_t]] [[low_bits]] [[const_neg1x2]]
9191
; CHECK: [[ans_bits:%.+]] = OpSelect [[u32x2_t]] [[should_use_high]] [[high_bits]] [[low_bits]]
92-
; CHECK: [[ans_offset:%.+]] = OpSelect [[u32x2_t]] [[should_use_high]] [[const_thirty_twox2]] [[const_zerox2]]
92+
; CHECK: [[ans_offset:%.+]] = OpSelect [[u32x2_t]] [[should_use_high]] [[const_32x2]] [[const_0x2]]
9393
; CHECK: [[ret:%.+]] = OpIAdd [[u32x2_t]] [[ans_offset]] [[ans_bits]]
9494
; CHECK: OpReturnValue [[ret]]
9595
%elt.firstbitlow = call <2 x i32> @llvm.spv.firstbitlow.v2i64(<2 x i64> %a)

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