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[CodeGen] Port two-address-instructions to new pass manager
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+170
-73
lines changed

‎llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h

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//===- llvm/CodeGen/TwoAddressInstructionPass.h -----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_TWOADDRESSINSTRUCTIONPASS_H
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#define LLVM_CODEGEN_TWOADDRESSINSTRUCTIONPASS_H
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#include "llvm/CodeGen/MachinePassManager.h"
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namespace llvm {
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class TwoAddressInstructionPass
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: public PassInfoMixin<TwoAddressInstructionPass> {
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public:
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PreservedAnalyses run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM);
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MachineFunctionProperties getSetProperties() {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::TiedOpsRewritten);
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}
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};
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} // namespace llvm
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#endif // LLVM_CODEGEN_TWOADDRESSINSTRUCTIONPASS_H

‎llvm/include/llvm/InitializePasses.h

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@@ -298,7 +298,7 @@ void initializeTargetLibraryInfoWrapperPassPass(PassRegistry&);
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void initializeTargetPassConfigPass(PassRegistry&);
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void initializeTargetTransformInfoWrapperPassPass(PassRegistry&);
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void initializeTLSVariableHoistLegacyPassPass(PassRegistry &);
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void initializeTwoAddressInstructionPassPass(PassRegistry&);
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void initializeTwoAddressInstructionLegacyPassPass(PassRegistry &);
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void initializeTypeBasedAAWrapperPassPass(PassRegistry&);
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void initializeTypePromotionLegacyPass(PassRegistry&);
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void initializeInitUndefPass(PassRegistry &);

‎llvm/include/llvm/Passes/CodeGenPassBuilder.h

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#include "llvm/CodeGen/SjLjEHPrepare.h"
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#include "llvm/CodeGen/StackProtector.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TwoAddressInstructionPass.h"
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#include "llvm/CodeGen/UnreachableBlockElim.h"
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#include "llvm/CodeGen/WasmEHPrepare.h"
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#include "llvm/CodeGen/WinEHPrepare.h"

‎llvm/include/llvm/Passes/MachinePassRegistry.def

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@@ -148,6 +148,7 @@ MACHINE_FUNCTION_PASS("print<slot-indexes>", SlotIndexesPrinterPass(dbgs()))
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MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
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RequireAllMachineFunctionPropertiesPass())
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MACHINE_FUNCTION_PASS("trigger-verifier-error", TriggerVerifierErrorPass())
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MACHINE_FUNCTION_PASS("two-address-instruction", TwoAddressInstructionPass())
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MACHINE_FUNCTION_PASS("verify", MachineVerifierPass())
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#undef MACHINE_FUNCTION_PASS
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@@ -258,7 +259,6 @@ DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass)
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DUMMY_MACHINE_FUNCTION_PASS("stack-slot-coloring", StackSlotColoringPass)
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DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass)
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DUMMY_MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass)
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DUMMY_MACHINE_FUNCTION_PASS("twoaddressinstruction", TwoAddressInstructionPass)
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DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass)
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DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass)
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DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass)

‎llvm/lib/CodeGen/CodeGen.cpp

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@@ -132,7 +132,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
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initializeStripDebugMachineModulePass(Registry);
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initializeTailDuplicatePass(Registry);
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initializeTargetPassConfigPass(Registry);
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initializeTwoAddressInstructionPassPass(Registry);
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initializeTwoAddressInstructionLegacyPassPass(Registry);
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initializeTypePromotionLegacyPass(Registry);
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initializeUnpackMachineBundlesPass(Registry);
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initializeUnreachableBlockElimLegacyPassPass(Registry);

‎llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

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‎llvm/lib/Passes/PassBuilder.cpp

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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/StackProtector.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TwoAddressInstructionPass.h"
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#include "llvm/CodeGen/TypePromotion.h"
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#include "llvm/CodeGen/WasmEHPrepare.h"
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#include "llvm/CodeGen/WinEHPrepare.h"

‎llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-linux -run-pass=twoaddressinstruction -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple=aarch64-unknown-linux --passes=two-address-instruction %s -o - | FileCheck %s
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# REQUIRES: aarch64-registered-target
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# Verify that the register class is correctly constrained after the twoaddress replacement

‎llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -early-live-intervals -run-pass=liveintervals -run-pass=twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -passes='require<live-intervals>,two-address-instruction' -o - %s | FileCheck %s
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---
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name: dyn_extract_v7f64_v_v

‎llvm/test/CodeGen/AMDGPU/early-lis-two-address-partial-def.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=liveintervals -run-pass=twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX90A %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a --passes='require<live-intervals>,two-address-instruction' -o - %s | FileCheck --check-prefix=GFX90A %s
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---
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name: aligned_partial_vgpr_64

‎llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir

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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX10 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - -early-live-intervals | FileCheck --check-prefixes=GFX10 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 %s --passes=two-address-instruction -o - | FileCheck --check-prefixes=GFX10 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 %s --passes=two-address-instruction -o - -early-live-intervals | FileCheck --check-prefixes=GFX10 %s
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# GFX10-LABEL: name: test_fmamk_reg_imm_f16
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# GFX10: %2:vgpr_32 = IMPLICIT_DEF

‎llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s --passes=two-address-instruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s
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---
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name: test_fmamk_reg_imm_f16

‎llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir

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# RUN: llc -mtriple=amdgcn -mcpu=gfx90a %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx90a %s -run-pass twoaddressinstruction -verify-machineinstrs -o - -early-live-intervals | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx90a %s --passes=two-address-instruction -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx90a %s --passes=two-address-instruction -o - -early-live-intervals | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: test_fmamk_reg_imm_f64
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# GCN: V_FMA_F64_e64 0, killed %0, 0, %2, 0, killed %1, 0, 0, implicit $mode, implicit $exec

‎llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir

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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - -early-live-intervals | FileCheck --check-prefixes=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - -early-live-intervals | FileCheck --check-prefixes=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 %s --passes=two-address-instruction -o - | FileCheck --check-prefixes=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s --passes=two-address-instruction -o - | FileCheck --check-prefixes=GCN %s
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# GCN-LABEL: name: test_fmamk_reg_imm_f32
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# GCN: %2:vgpr_32 = IMPLICIT_DEF

‎llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir

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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - -early-live-intervals | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 %s --passes=two-address-instruction -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: test_madmk_reg_imm_f32
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# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec

‎llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir

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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - -early-live-intervals | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s --passes=two-address-instruction -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: test_v_wmma_f32_16x16x16_f16_twoaddr_w32
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# GCN: early-clobber %2:vreg_256 = V_WMMA_F32_16X16X16_F16_threeaddr_w32 8, killed %1, 8, killed %1, 8, %0, 0, 0, implicit $exec

‎llvm/test/CodeGen/Hexagon/two-addr-tied-subregs.mir

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# RUN: llc -march hexagon -run-pass livevars -run-pass twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march hexagon --passes='require<live-vars>,two-address-instruction' -o - %s | FileCheck %s
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###############################################################################

‎llvm/test/CodeGen/X86/distancemap.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -o - -mtriple=x86_64-unknown-linux -run-pass=twoaddressinstruction -verify-machineinstrs | FileCheck %s
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# RUN: llc %s -o - -mtriple=x86_64-unknown-linux --passes=two-address-instruction | FileCheck %s
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# In TwoAddressInstructionPass, new instructions should be added to DistanceMap.
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# In this case, function convertInstTo3Addr is called on the first ADD

‎llvm/test/CodeGen/X86/statepoint-vreg-twoaddr.mir

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# RUN: llc -x mir -run-pass=twoaddressinstruction < %s | FileCheck %s
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# RUN: llc -x mir --passes=two-address-instruction < %s | FileCheck %s
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# This test checks that TwoAddressInstruction pass does not create redundate COPY
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# instruction for STATEPOINT tied operands.

‎llvm/test/CodeGen/X86/twoaddr-mul2.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-unknown -mcpu=haswell -run-pass=twoaddressinstruction -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple=x86_64-unknown -mcpu=haswell --passes=two-address-instruction -verify-machineinstrs %s -o - | FileCheck %s
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# Check that we don't have any uses of [[COPY]] after it is killed.
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---

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