Skip to content
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.

Commit 53c0e80

Browse files
fhahnfhahn
authoredFeb 16, 2024
[SROA] Use !tbaa instead of !tbaa.struct if op matches field. (#81289)
If a split memory access introduced by SROA accesses precisely a single field of the original operation's !tbaa.struct, use the !tbaa tag for the accessed field directly instead of the full !tbaa.struct. InstCombine already had a similar logic. Motivation for this and follow-on patches is to improve codegen for libc++, where using memcpy limits optimizations, like vectorization for code iteration over std::vector<std::complex<float>>: https://godbolt.org/z/f3vqYos3c Depends on #81285.
1 parent 17d8a84 commit 53c0e80

File tree

6 files changed

+115
-73
lines changed

6 files changed

+115
-73
lines changed
 

‎clang/test/CodeGen/aarch64-ABI-align-packed.c

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ struct non_packed_struct gs_non_packed_struct;
5959
// CHECK-NEXT: entry:
6060
// CHECK-NEXT: [[S_NON_PACKED_STRUCT_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_NON_PACKED_STRUCT_COERCE]], 0
6161
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2:![0-9]+]]
62-
// CHECK-NEXT: store <8 x i16> [[S_NON_PACKED_STRUCT_COERCE_FCA_0_EXTRACT]], ptr @gs_non_packed_struct, align 16, !tbaa.struct [[TBAA_STRUCT6:![0-9]+]]
62+
// CHECK-NEXT: store <8 x i16> [[S_NON_PACKED_STRUCT_COERCE_FCA_0_EXTRACT]], ptr @gs_non_packed_struct, align 16, !tbaa [[TBAA6:![0-9]+]]
6363
// CHECK-NEXT: ret void
6464
__attribute__((noinline)) void named_arg_non_packed_struct(double d0, double d1, double d2, double d3,
6565
double d4, double d5, double d6, double d7,
@@ -114,7 +114,7 @@ struct packed_struct gs_packed_struct;
114114
// CHECK-NEXT: entry:
115115
// CHECK-NEXT: [[S_PACKED_STRUCT_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_PACKED_STRUCT_COERCE]], 0
116116
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
117-
// CHECK-NEXT: store <8 x i16> [[S_PACKED_STRUCT_COERCE_FCA_0_EXTRACT]], ptr @gs_packed_struct, align 1, !tbaa.struct [[TBAA_STRUCT6]]
117+
// CHECK-NEXT: store <8 x i16> [[S_PACKED_STRUCT_COERCE_FCA_0_EXTRACT]], ptr @gs_packed_struct, align 1, !tbaa [[TBAA6]]
118118
// CHECK-NEXT: ret void
119119
__attribute__((noinline)) void named_arg_packed_struct(double d0, double d1, double d2, double d3,
120120
double d4, double d5, double d6, double d7,
@@ -169,7 +169,7 @@ struct packed_member gs_packed_member;
169169
// CHECK-NEXT: entry:
170170
// CHECK-NEXT: [[S_PACKED_MEMBER_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_PACKED_MEMBER_COERCE]], 0
171171
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
172-
// CHECK-NEXT: store <8 x i16> [[S_PACKED_MEMBER_COERCE_FCA_0_EXTRACT]], ptr @gs_packed_member, align 1, !tbaa.struct [[TBAA_STRUCT6]]
172+
// CHECK-NEXT: store <8 x i16> [[S_PACKED_MEMBER_COERCE_FCA_0_EXTRACT]], ptr @gs_packed_member, align 1, !tbaa [[TBAA6]]
173173
// CHECK-NEXT: ret void
174174
__attribute__((noinline)) void named_arg_packed_member(double d0, double d1, double d2, double d3,
175175
double d4, double d5, double d6, double d7,
@@ -224,7 +224,7 @@ struct aligned_struct_8 gs_aligned_struct_8;
224224
// CHECK-NEXT: entry:
225225
// CHECK-NEXT: [[S_ALIGNED_STRUCT_8_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_ALIGNED_STRUCT_8_COERCE]], 0
226226
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
227-
// CHECK-NEXT: store <8 x i16> [[S_ALIGNED_STRUCT_8_COERCE_FCA_0_EXTRACT]], ptr @gs_aligned_struct_8, align 16, !tbaa.struct [[TBAA_STRUCT6]]
227+
// CHECK-NEXT: store <8 x i16> [[S_ALIGNED_STRUCT_8_COERCE_FCA_0_EXTRACT]], ptr @gs_aligned_struct_8, align 16, !tbaa [[TBAA6]]
228228
// CHECK-NEXT: ret void
229229
__attribute__((noinline)) void named_arg_aligned_struct_8(double d0, double d1, double d2, double d3,
230230
double d4, double d5, double d6, double d7,
@@ -279,7 +279,7 @@ struct aligned_member_8 gs_aligned_member_8;
279279
// CHECK-NEXT: entry:
280280
// CHECK-NEXT: [[S_ALIGNED_MEMBER_8_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_ALIGNED_MEMBER_8_COERCE]], 0
281281
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
282-
// CHECK-NEXT: store <8 x i16> [[S_ALIGNED_MEMBER_8_COERCE_FCA_0_EXTRACT]], ptr @gs_aligned_member_8, align 16, !tbaa.struct [[TBAA_STRUCT6]]
282+
// CHECK-NEXT: store <8 x i16> [[S_ALIGNED_MEMBER_8_COERCE_FCA_0_EXTRACT]], ptr @gs_aligned_member_8, align 16, !tbaa [[TBAA6]]
283283
// CHECK-NEXT: ret void
284284
__attribute__((noinline)) void named_arg_aligned_member_8(double d0, double d1, double d2, double d3,
285285
double d4, double d5, double d6, double d7,
@@ -334,7 +334,7 @@ struct pragma_packed_struct_8 gs_pragma_packed_struct_8;
334334
// CHECK-NEXT: entry:
335335
// CHECK-NEXT: [[S_PRAGMA_PACKED_STRUCT_8_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_PRAGMA_PACKED_STRUCT_8_COERCE]], 0
336336
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
337-
// CHECK-NEXT: store <8 x i16> [[S_PRAGMA_PACKED_STRUCT_8_COERCE_FCA_0_EXTRACT]], ptr @gs_pragma_packed_struct_8, align 8, !tbaa.struct [[TBAA_STRUCT6]]
337+
// CHECK-NEXT: store <8 x i16> [[S_PRAGMA_PACKED_STRUCT_8_COERCE_FCA_0_EXTRACT]], ptr @gs_pragma_packed_struct_8, align 8, !tbaa [[TBAA6]]
338338
// CHECK-NEXT: ret void
339339
__attribute__((noinline)) void named_arg_pragma_packed_struct_8(double d0, double d1, double d2, double d3,
340340
double d4, double d5, double d6, double d7,
@@ -389,7 +389,7 @@ struct pragma_packed_struct_4 gs_pragma_packed_struct_4;
389389
// CHECK-NEXT: entry:
390390
// CHECK-NEXT: [[S_PRAGMA_PACKED_STRUCT_4_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_PRAGMA_PACKED_STRUCT_4_COERCE]], 0
391391
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
392-
// CHECK-NEXT: store <8 x i16> [[S_PRAGMA_PACKED_STRUCT_4_COERCE_FCA_0_EXTRACT]], ptr @gs_pragma_packed_struct_4, align 4, !tbaa.struct [[TBAA_STRUCT6]]
392+
// CHECK-NEXT: store <8 x i16> [[S_PRAGMA_PACKED_STRUCT_4_COERCE_FCA_0_EXTRACT]], ptr @gs_pragma_packed_struct_4, align 4, !tbaa [[TBAA6]]
393393
// CHECK-NEXT: ret void
394394
__attribute__((noinline)) void named_arg_pragma_packed_struct_4(double d0, double d1, double d2, double d3,
395395
double d4, double d5, double d6, double d7,
@@ -436,3 +436,10 @@ void test_pragma_packed_struct_4() {
436436
named_arg_pragma_packed_struct_4(1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 2.0, s_pragma_packed_struct_4);
437437
variadic_pragma_packed_struct_4(1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 2.0, s_pragma_packed_struct_4);
438438
}
439+
//.
440+
// CHECK: [[TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
441+
// CHECK: [[META3]] = !{!"double", [[META4:![0-9]+]], i64 0}
442+
// CHECK: [[META4]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
443+
// CHECK: [[META5]] = !{!"Simple C/C++ TBAA"}
444+
// CHECK: [[TBAA6]] = !{[[META4]], [[META4]], i64 0}
445+
//.

‎llvm/include/llvm/IR/Metadata.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -849,6 +849,9 @@ struct AAMDNodes {
849849
/// If his AAMDNode has !tbaa.struct and \p AccessSize matches the size of the
850850
/// field at offset 0, get the TBAA tag describing the accessed field.
851851
AAMDNodes adjustForAccess(unsigned AccessSize);
852+
AAMDNodes adjustForAccess(size_t Offset, Type *AccessTy,
853+
const DataLayout &DL);
854+
AAMDNodes adjustForAccess(size_t Offset, unsigned AccessSize);
852855
};
853856

854857
// Specialize DenseMapInfo for AAMDNodes.

‎llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -833,3 +833,20 @@ AAMDNodes AAMDNodes::adjustForAccess(unsigned AccessSize) {
833833
}
834834
return New;
835835
}
836+
837+
AAMDNodes AAMDNodes::adjustForAccess(size_t Offset, Type *AccessTy,
838+
const DataLayout &DL) {
839+
AAMDNodes New = shift(Offset);
840+
if (!DL.typeSizeEqualsStoreSize(AccessTy))
841+
return New;
842+
TypeSize Size = DL.getTypeStoreSize(AccessTy);
843+
if (Size.isScalable())
844+
return New;
845+
846+
return New.adjustForAccess(Size.getKnownMinValue());
847+
}
848+
849+
AAMDNodes AAMDNodes::adjustForAccess(size_t Offset, unsigned AccessSize) {
850+
AAMDNodes New = shift(Offset);
851+
return New.adjustForAccess(AccessSize);
852+
}

‎llvm/lib/Transforms/Scalar/SROA.cpp

Lines changed: 33 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2914,7 +2914,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
29142914

29152915
// Do this after copyMetadataForLoad() to preserve the TBAA shift.
29162916
if (AATags)
2917-
NewLI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
2917+
NewLI->setAAMetadata(AATags.adjustForAccess(
2918+
NewBeginOffset - BeginOffset, NewLI->getType(), DL));
29182919

29192920
// Try to preserve nonnull metadata
29202921
V = NewLI;
@@ -2935,8 +2936,11 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
29352936
LoadInst *NewLI =
29362937
IRB.CreateAlignedLoad(TargetTy, getNewAllocaSlicePtr(IRB, LTy),
29372938
getSliceAlign(), LI.isVolatile(), LI.getName());
2939+
29382940
if (AATags)
2939-
NewLI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
2941+
NewLI->setAAMetadata(AATags.adjustForAccess(
2942+
NewBeginOffset - BeginOffset, NewLI->getType(), DL));
2943+
29402944
if (LI.isVolatile())
29412945
NewLI->setAtomic(LI.getOrdering(), LI.getSyncScopeID());
29422946
NewLI->copyMetadata(LI, {LLVMContext::MD_mem_parallel_loop_access,
@@ -3011,7 +3015,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
30113015
Store->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
30123016
LLVMContext::MD_access_group});
30133017
if (AATags)
3014-
Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3018+
Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3019+
V->getType(), DL));
30153020
Pass.DeadInsts.push_back(&SI);
30163021

30173022
// NOTE: Careful to use OrigV rather than V.
@@ -3038,7 +3043,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
30383043
Store->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
30393044
LLVMContext::MD_access_group});
30403045
if (AATags)
3041-
Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3046+
Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3047+
V->getType(), DL));
30423048

30433049
migrateDebugInfo(&OldAI, IsSplit, NewBeginOffset * 8, SliceSize * 8, &SI,
30443050
Store, Store->getPointerOperand(),
@@ -3098,7 +3104,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
30983104
NewSI->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
30993105
LLVMContext::MD_access_group});
31003106
if (AATags)
3101-
NewSI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3107+
NewSI->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3108+
V->getType(), DL));
31023109
if (SI.isVolatile())
31033110
NewSI->setAtomic(SI.getOrdering(), SI.getSyncScopeID());
31043111
if (NewSI->isAtomic())
@@ -3200,12 +3207,14 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
32003207
// a single value type, just emit a memset.
32013208
if (!CanContinue) {
32023209
Type *SizeTy = II.getLength()->getType();
3203-
Constant *Size = ConstantInt::get(SizeTy, NewEndOffset - NewBeginOffset);
3210+
unsigned Sz = NewEndOffset - NewBeginOffset;
3211+
Constant *Size = ConstantInt::get(SizeTy, Sz);
32043212
MemIntrinsic *New = cast<MemIntrinsic>(IRB.CreateMemSet(
32053213
getNewAllocaSlicePtr(IRB, OldPtr->getType()), II.getValue(), Size,
32063214
MaybeAlign(getSliceAlign()), II.isVolatile()));
32073215
if (AATags)
3208-
New->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3216+
New->setAAMetadata(
3217+
AATags.adjustForAccess(NewBeginOffset - BeginOffset, Sz));
32093218

32103219
migrateDebugInfo(&OldAI, IsSplit, NewBeginOffset * 8, SliceSize * 8, &II,
32113220
New, New->getRawDest(), nullptr, DL);
@@ -3281,7 +3290,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
32813290
New->copyMetadata(II, {LLVMContext::MD_mem_parallel_loop_access,
32823291
LLVMContext::MD_access_group});
32833292
if (AATags)
3284-
New->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3293+
New->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3294+
V->getType(), DL));
32853295

32863296
migrateDebugInfo(&OldAI, IsSplit, NewBeginOffset * 8, SliceSize * 8, &II,
32873297
New, New->getPointerOperand(), V, DL);
@@ -3486,7 +3496,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
34863496
Load->copyMetadata(II, {LLVMContext::MD_mem_parallel_loop_access,
34873497
LLVMContext::MD_access_group});
34883498
if (AATags)
3489-
Load->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3499+
Load->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3500+
Load->getType(), DL));
34903501
Src = Load;
34913502
}
34923503

@@ -3508,7 +3519,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
35083519
Store->copyMetadata(II, {LLVMContext::MD_mem_parallel_loop_access,
35093520
LLVMContext::MD_access_group});
35103521
if (AATags)
3511-
Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3522+
Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3523+
Src->getType(), DL));
35123524

35133525
APInt Offset(DL.getIndexTypeSizeInBits(DstPtr->getType()), 0);
35143526
if (IsDest) {
@@ -3836,7 +3848,8 @@ class AggLoadStoreRewriter : public InstVisitor<AggLoadStoreRewriter, bool> {
38363848
DL.getIndexSizeInBits(Ptr->getType()->getPointerAddressSpace()), 0);
38373849
if (AATags &&
38383850
GEPOperator::accumulateConstantOffset(BaseTy, GEPIndices, DL, Offset))
3839-
Load->setAAMetadata(AATags.shift(Offset.getZExtValue()));
3851+
Load->setAAMetadata(
3852+
AATags.adjustForAccess(Offset.getZExtValue(), Load->getType(), DL));
38403853

38413854
Agg = IRB.CreateInsertValue(Agg, Load, Indices, Name + ".insert");
38423855
LLVM_DEBUG(dbgs() << " to: " << *Load << "\n");
@@ -3887,8 +3900,10 @@ class AggLoadStoreRewriter : public InstVisitor<AggLoadStoreRewriter, bool> {
38873900
APInt Offset(
38883901
DL.getIndexSizeInBits(Ptr->getType()->getPointerAddressSpace()), 0);
38893902
GEPOperator::accumulateConstantOffset(BaseTy, GEPIndices, DL, Offset);
3890-
if (AATags)
3891-
Store->setAAMetadata(AATags.shift(Offset.getZExtValue()));
3903+
if (AATags) {
3904+
Store->setAAMetadata(AATags.adjustForAccess(
3905+
Offset.getZExtValue(), ExtractValue->getType(), DL));
3906+
}
38923907

38933908
// migrateDebugInfo requires the base Alloca. Walk to it from this gep.
38943909
// If we cannot (because there's an intervening non-const or unbounded
@@ -4542,6 +4557,7 @@ bool SROA::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
45424557

45434558
Value *StoreBasePtr = SI->getPointerOperand();
45444559
IRB.SetInsertPoint(SI);
4560+
AAMDNodes AATags = SI->getAAMetadata();
45454561

45464562
LLVM_DEBUG(dbgs() << " Splitting store of load: " << *SI << "\n");
45474563

@@ -4561,6 +4577,10 @@ bool SROA::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
45614577
PStore->copyMetadata(*SI, {LLVMContext::MD_mem_parallel_loop_access,
45624578
LLVMContext::MD_access_group,
45634579
LLVMContext::MD_DIAssignID});
4580+
4581+
if (AATags)
4582+
PStore->setAAMetadata(
4583+
AATags.adjustForAccess(PartOffset, PLoad->getType(), DL));
45644584
LLVM_DEBUG(dbgs() << " +" << PartOffset << ":" << *PStore << "\n");
45654585
}
45664586

‎llvm/test/Transforms/SROA/tbaa-struct2.ll

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,9 @@ define double @bar(ptr %wishart) {
1313
; CHECK-NEXT: [[TMP_SROA_3:%.*]] = alloca [4 x i8], align 4
1414
; CHECK-NEXT: [[TMP_SROA_0_0_COPYLOAD:%.*]] = load double, ptr [[WISHART:%.*]], align 8, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
1515
; CHECK-NEXT: [[TMP_SROA_2_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 8
16-
; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
16+
; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa [[TBAA5:![0-9]+]]
1717
; CHECK-NEXT: [[TMP_SROA_3_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 12
18-
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT8:![0-9]+]]
18+
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
1919
; CHECK-NEXT: [[CALL:%.*]] = call double @subcall(double [[TMP_SROA_0_0_COPYLOAD]], i32 [[TMP_SROA_2_0_COPYLOAD]])
2020
; CHECK-NEXT: ret double [[CALL]]
2121
;
@@ -38,15 +38,14 @@ define double @bar(ptr %wishart) {
3838
;.
3939
; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
4040
;.
41-
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, !1, i64 8, i64 4, !5}
42-
; CHECK: [[META1:![0-9]+]] = !{!2, !2, i64 0}
43-
; CHECK: [[META2:![0-9]+]] = !{!"double", !3, i64 0}
44-
; CHECK: [[META3:![0-9]+]] = !{!"omnipotent char", !4, i64 0}
45-
; CHECK: [[META4:![0-9]+]] = !{!"Simple C++ TBAA"}
46-
; CHECK: [[META5:![0-9]+]] = !{!6, !6, i64 0}
47-
; CHECK: [[META6:![0-9]+]] = !{!"int", !3, i64 0}
48-
; CHECK: [[TBAA_STRUCT7]] = !{i64 0, i64 4, !5}
49-
; CHECK: [[TBAA_STRUCT8]] = !{}
41+
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, [[META1:![0-9]+]], i64 8, i64 4, [[TBAA5]]}
42+
; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
43+
; CHECK: [[META2]] = !{!"double", [[META3:![0-9]+]], i64 0}
44+
; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
45+
; CHECK: [[META4]] = !{!"Simple C++ TBAA"}
46+
; CHECK: [[TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
47+
; CHECK: [[META6]] = !{!"int", [[META3]], i64 0}
48+
; CHECK: [[TBAA_STRUCT7]] = !{}
5049
;.
5150
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
5251
; CHECK-MODIFY-CFG: {{.*}}

‎llvm/test/Transforms/SROA/tbaa-struct3.ll

Lines changed: 38 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,9 @@ define void @load_store_transfer_split_struct_tbaa_2_float(ptr dereferenceable(2
1010
; CHECK-NEXT: entry:
1111
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[A]] to i32
1212
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[B]] to i32
13-
; CHECK-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4
13+
; CHECK-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
1414
; CHECK-NEXT: [[RES_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[RES]], i64 4
15-
; CHECK-NEXT: store i32 [[TMP1]], ptr [[RES_SROA_IDX]], align 4
15+
; CHECK-NEXT: store i32 [[TMP1]], ptr [[RES_SROA_IDX]], align 4, !tbaa [[TBAA1:![0-9]+]]
1616
; CHECK-NEXT: [[P:%.*]] = load ptr, ptr [[RES]], align 8
1717
; CHECK-NEXT: ret void
1818
;
@@ -32,9 +32,9 @@ define void @memcpy_transfer(ptr dereferenceable(24) %res, float %a, float %b) {
3232
; CHECK-SAME: ptr dereferenceable(24) [[RES:%.*]], float [[A:%.*]], float [[B:%.*]]) {
3333
; CHECK-NEXT: entry:
3434
; CHECK-NEXT: [[L_PTR:%.*]] = load ptr, ptr [[RES]], align 8
35-
; CHECK-NEXT: store float [[A]], ptr [[L_PTR]], align 1, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
35+
; CHECK-NEXT: store float [[A]], ptr [[L_PTR]], align 1, !tbaa.struct [[TBAA_STRUCT0]]
3636
; CHECK-NEXT: [[TMP_SROA_2_0_L_PTR_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[L_PTR]], i64 4
37-
; CHECK-NEXT: store float [[B]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5:![0-9]+]]
37+
; CHECK-NEXT: store float [[B]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa [[TBAA1]]
3838
; CHECK-NEXT: ret void
3939
;
4040
entry:
@@ -56,7 +56,7 @@ define void @memcpy_transfer_tbaa_field_and_size_do_not_align(ptr dereferenceabl
5656
; CHECK-NEXT: [[TMP_SROA_2_0_L_PTR_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[L_PTR]], i64 4
5757
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[B]] to i32
5858
; CHECK-NEXT: [[TMP_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[TMP0]] to i16
59-
; CHECK-NEXT: store i16 [[TMP_SROA_2_0_EXTRACT_TRUNC]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5]]
59+
; CHECK-NEXT: store i16 [[TMP_SROA_2_0_EXTRACT_TRUNC]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5:![0-9]+]]
6060
; CHECK-NEXT: ret void
6161
;
6262
entry:
@@ -100,7 +100,7 @@ define void @store_vector_part_first(ptr %y2, float %f) {
100100
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
101101
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 8, !tbaa.struct [[TBAA_STRUCT6:![0-9]+]]
102102
; CHECK-NEXT: [[X7_SROA_2_0_Y2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[Y2]], i64 8
103-
; CHECK-NEXT: store float [[F]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 8, !tbaa.struct [[TBAA_STRUCT5]]
103+
; CHECK-NEXT: store float [[F]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 8, !tbaa [[TBAA1]]
104104
; CHECK-NEXT: ret void
105105
;
106106
%x7 = alloca { float, float, float, float }
@@ -118,7 +118,7 @@ define void @store_vector_part_second(ptr %y2, float %f) {
118118
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
119119
; CHECK-NEXT: store float [[F]], ptr [[Y2]], align 8, !tbaa.struct [[TBAA_STRUCT9:![0-9]+]]
120120
; CHECK-NEXT: [[X7_SROA_2_0_Y2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[Y2]], i64 4
121-
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 4, !tbaa.struct [[TBAA_STRUCT10:![0-9]+]]
121+
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 4, !tbaa [[TBAA7:![0-9]+]]
122122
; CHECK-NEXT: ret void
123123
;
124124
%x7 = alloca { float, float, float, float }
@@ -134,7 +134,7 @@ define void @store_vector_single(ptr %y2, float %f) {
134134
; CHECK-LABEL: define void @store_vector_single(
135135
; CHECK-SAME: ptr [[Y2:%.*]], float [[F:%.*]]) {
136136
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
137-
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 4, !tbaa.struct [[TBAA_STRUCT11:![0-9]+]]
137+
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 4, !tbaa.struct [[TBAA_STRUCT10:![0-9]+]]
138138
; CHECK-NEXT: ret void
139139
;
140140
%x7 = alloca { float, float }
@@ -161,8 +161,8 @@ define void @memset(ptr %dst, ptr align 8 %src) {
161161
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 1 [[A_SROA_4_0_SRC_SROA_IDX]], i32 10, i1 false)
162162
; CHECK-NEXT: store i16 1, ptr [[A_SROA_3]], align 2
163163
; CHECK-NEXT: [[A_SROA_0_1_A_1_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 1
164-
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_1_A_1_SROA_IDX2]], i8 42, i32 6, i1 false), !tbaa.struct [[TBAA_STRUCT12:![0-9]+]]
165-
; CHECK-NEXT: store i16 10794, ptr [[A_SROA_3]], align 2, !tbaa.struct [[TBAA_STRUCT13:![0-9]+]]
164+
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_1_A_1_SROA_IDX2]], i8 42, i32 6, i1 false), !tbaa.struct [[TBAA_STRUCT11:![0-9]+]]
165+
; CHECK-NEXT: store i16 10794, ptr [[A_SROA_3]], align 2, !tbaa [[TBAA1]]
166166
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 7, i1 true)
167167
; CHECK-NEXT: [[A_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 7
168168
; CHECK-NEXT: [[A_SROA_3_0_A_SROA_3_0_COPYLOAD1:%.*]] = load volatile i16, ptr [[A_SROA_3]], align 2
@@ -199,8 +199,8 @@ define void @memset2(ptr %dst, ptr align 8 %src) {
199199
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 2 [[A_SROA_4_0_SRC_SROA_IDX]], i32 90, i1 false)
200200
; CHECK-NEXT: store i8 1, ptr [[A_SROA_3]], align 1
201201
; CHECK-NEXT: [[A_SROA_0_202_A_202_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 202
202-
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_202_A_202_SROA_IDX2]], i8 42, i32 7, i1 false), !tbaa.struct [[TBAA_STRUCT14:![0-9]+]]
203-
; CHECK-NEXT: store i8 42, ptr [[A_SROA_3]], align 1, !tbaa.struct [[TBAA_STRUCT15:![0-9]+]]
202+
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_202_A_202_SROA_IDX2]], i8 42, i32 7, i1 false), !tbaa.struct [[TBAA_STRUCT12:![0-9]+]]
203+
; CHECK-NEXT: store i8 42, ptr [[A_SROA_3]], align 1, !tbaa [[TBAA7]]
204204
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 209, i1 true)
205205
; CHECK-NEXT: [[A_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 209
206206
; CHECK-NEXT: [[A_SROA_3_0_A_SROA_3_0_COPYLOAD1:%.*]] = load volatile i8, ptr [[A_SROA_3]], align 1
@@ -240,7 +240,7 @@ define void @slice_store_v2i8_1(ptr %dst, ptr %dst.2, ptr %src) {
240240
; CHECK-NEXT: [[A_SROA_2_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 6
241241
; CHECK-NEXT: [[A_SROA_2_SROA_0_0_COPYLOAD:%.*]] = load <2 x i8>, ptr [[A_SROA_2_0_SRC_SROA_IDX]], align 2
242242
; CHECK-NEXT: store <2 x i8> [[A_SROA_2_SROA_0_0_COPYLOAD]], ptr [[A_SROA_2_SROA_0]], align 4
243-
; CHECK-NEXT: store <2 x i8> bitcast (<1 x i16> <i16 123> to <2 x i8>), ptr [[A_SROA_2_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT16:![0-9]+]]
243+
; CHECK-NEXT: store <2 x i8> bitcast (<1 x i16> <i16 123> to <2 x i8>), ptr [[A_SROA_2_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT13:![0-9]+]]
244244
; CHECK-NEXT: [[A_SROA_2_SROA_0_0_A_SROA_2_SROA_0_0_A_SROA_2_6_V_4:%.*]] = load <2 x i8>, ptr [[A_SROA_2_SROA_0]], align 4
245245
; CHECK-NEXT: store <2 x i8> [[A_SROA_2_SROA_0_0_A_SROA_2_SROA_0_0_A_SROA_2_6_V_4]], ptr [[DST_2]], align 2
246246
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 6, i1 true)
@@ -279,8 +279,8 @@ define void @slice_store_v2i8_2(ptr %dst, ptr %dst.2, ptr %src) {
279279
; CHECK-NEXT: store i8 [[A_SROA_0_SROA_4_1_COPYLOAD]], ptr [[A_SROA_0_SROA_4]], align 1
280280
; CHECK-NEXT: [[A_SROA_4_1_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 3
281281
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 1 [[A_SROA_4_1_SRC_SROA_IDX]], i32 5, i1 false)
282-
; CHECK-NEXT: store <2 x i8> zeroinitializer, ptr [[A_SROA_0_SROA_1]], align 2, !tbaa.struct [[TBAA_STRUCT17:![0-9]+]]
283-
; CHECK-NEXT: store i8 0, ptr [[A_SROA_0_SROA_4]], align 1, !tbaa.struct [[TBAA_STRUCT18:![0-9]+]]
282+
; CHECK-NEXT: store <2 x i8> zeroinitializer, ptr [[A_SROA_0_SROA_1]], align 2, !tbaa.struct [[TBAA_STRUCT14:![0-9]+]]
283+
; CHECK-NEXT: store i8 0, ptr [[A_SROA_0_SROA_4]], align 1, !tbaa [[TBAA1]]
284284
; CHECK-NEXT: [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_A_SROA_0_1_V_4:%.*]] = load <2 x i8>, ptr [[A_SROA_0_SROA_1]], align 2
285285
; CHECK-NEXT: store <2 x i8> [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_A_SROA_0_1_V_4]], ptr [[DST_2]], align 2
286286
; CHECK-NEXT: [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_COPYLOAD3:%.*]] = load volatile <2 x i8>, ptr [[A_SROA_0_SROA_1]], align 2
@@ -317,7 +317,7 @@ define double @tbaa_struct_load(ptr %src, ptr %dst) {
317317
; CHECK-NEXT: [[TMP_SROA_3_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 8
318318
; CHECK-NEXT: [[TMP_SROA_3_0_COPYLOAD:%.*]] = load i64, ptr [[TMP_SROA_3_0_SRC_SROA_IDX]], align 8
319319
; CHECK-NEXT: store i64 [[TMP_SROA_3_0_COPYLOAD]], ptr [[TMP_SROA_3]], align 8
320-
; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_LG:%.*]] = load double, ptr [[TMP_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT10]]
320+
; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_LG:%.*]] = load double, ptr [[TMP_SROA_0]], align 8, !tbaa [[TBAA7]]
321321
; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_COPYLOAD1:%.*]] = load volatile double, ptr [[TMP_SROA_0]], align 8
322322
; CHECK-NEXT: store volatile double [[TMP_SROA_0_0_TMP_SROA_0_0_COPYLOAD1]], ptr [[DST]], align 8
323323
; CHECK-NEXT: [[TMP_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 8
@@ -356,7 +356,7 @@ define i32 @shorten_integer_store_multiple_fields(ptr %dst, ptr %dst.2, ptr %src
356356
; CHECK-SAME: ptr [[DST:%.*]], ptr [[DST_2:%.*]], ptr [[SRC:%.*]]) {
357357
; CHECK-NEXT: entry:
358358
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i32, align 4
359-
; CHECK-NEXT: store i32 123, ptr [[A_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT19:![0-9]+]]
359+
; CHECK-NEXT: store i32 123, ptr [[A_SROA_0]], align 4, !tbaa [[TBAA7]]
360360
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load i32, ptr [[A_SROA_0]], align 4
361361
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_COPYLOAD:%.*]] = load volatile i32, ptr [[A_SROA_0]], align 4
362362
; CHECK-NEXT: store volatile i32 [[A_SROA_0_0_A_SROA_0_0_COPYLOAD]], ptr [[DST]], align 1
@@ -393,7 +393,7 @@ define <2 x i16> @shorten_vector_store_single_fields(ptr %dst, ptr %dst.2, ptr %
393393
; CHECK-SAME: ptr [[DST:%.*]], ptr [[DST_2:%.*]], ptr [[SRC:%.*]]) {
394394
; CHECK-NEXT: entry:
395395
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca <2 x i32>, align 8
396-
; CHECK-NEXT: store <2 x i32> <i32 1, i32 2>, ptr [[A_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT19]]
396+
; CHECK-NEXT: store <2 x i32> <i32 1, i32 2>, ptr [[A_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT15:![0-9]+]]
397397
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load <2 x i16>, ptr [[A_SROA_0]], align 8
398398
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 8 [[A_SROA_0]], i32 4, i1 true)
399399
; CHECK-NEXT: ret <2 x i16> [[A_SROA_0_0_A_SROA_0_0_L]]
@@ -429,11 +429,11 @@ define i32 @split_load_with_tbaa_struct(i32 %x, ptr %src, ptr %dst) {
429429
; CHECK-NEXT: [[A3_SROA_5_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 9
430430
; CHECK-NEXT: [[A3_SROA_5_0_COPYLOAD:%.*]] = load i8, ptr [[A3_SROA_5_0_SRC_SROA_IDX]], align 1
431431
; CHECK-NEXT: store i8 [[A3_SROA_5_0_COPYLOAD]], ptr [[A3_SROA_5]], align 1
432-
; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD:%.*]] = load i16, ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT20:![0-9]+]]
432+
; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD:%.*]] = load i16, ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT16:![0-9]+]]
433433
; CHECK-NEXT: [[LOAD4_FCA_0_INSERT:%.*]] = insertvalue { i16, float, i8 } poison, i16 [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD]], 0
434-
; CHECK-NEXT: [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD:%.*]] = load float, ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT21:![0-9]+]]
434+
; CHECK-NEXT: [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD:%.*]] = load float, ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT17:![0-9]+]]
435435
; CHECK-NEXT: [[LOAD4_FCA_1_INSERT:%.*]] = insertvalue { i16, float, i8 } [[LOAD4_FCA_0_INSERT]], float [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD]], 1
436-
; CHECK-NEXT: [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD:%.*]] = load i8, ptr [[A3_SROA_4]], align 8, !tbaa.struct [[TBAA_STRUCT15]]
436+
; CHECK-NEXT: [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD:%.*]] = load i8, ptr [[A3_SROA_4]], align 8, !tbaa [[TBAA7]]
437437
; CHECK-NEXT: [[LOAD4_FCA_2_INSERT:%.*]] = insertvalue { i16, float, i8 } [[LOAD4_FCA_1_INSERT]], i8 [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD]], 2
438438
; CHECK-NEXT: [[UNWRAP2:%.*]] = extractvalue { i16, float, i8 } [[LOAD4_FCA_2_INSERT]], 1
439439
; CHECK-NEXT: [[VALCAST2:%.*]] = bitcast float [[UNWRAP2]] to i32
@@ -492,11 +492,11 @@ define i32 @split_store_with_tbaa_struct(i32 %x, ptr %src, ptr %dst) {
492492
; CHECK-NEXT: [[I_2:%.*]] = insertvalue { i16, float, i8 } [[I_1]], float 3.000000e+00, 1
493493
; CHECK-NEXT: [[I_3:%.*]] = insertvalue { i16, float, i8 } [[I_2]], i8 99, 2
494494
; CHECK-NEXT: [[I_3_FCA_0_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 0
495-
; CHECK-NEXT: store i16 [[I_3_FCA_0_EXTRACT]], ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT20]]
495+
; CHECK-NEXT: store i16 [[I_3_FCA_0_EXTRACT]], ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT16]]
496496
; CHECK-NEXT: [[I_3_FCA_1_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 1
497-
; CHECK-NEXT: store float [[I_3_FCA_1_EXTRACT]], ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT21]]
497+
; CHECK-NEXT: store float [[I_3_FCA_1_EXTRACT]], ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT17]]
498498
; CHECK-NEXT: [[I_3_FCA_2_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 2
499-
; CHECK-NEXT: store i8 [[I_3_FCA_2_EXTRACT]], ptr [[A3_SROA_4]], align 8, !tbaa.struct [[TBAA_STRUCT15]]
499+
; CHECK-NEXT: store i8 [[I_3_FCA_2_EXTRACT]], ptr [[A3_SROA_4]], align 8, !tbaa [[TBAA7]]
500500
; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_COPYLOAD1:%.*]] = load volatile i16, ptr [[A3_SROA_0]], align 8
501501
; CHECK-NEXT: store volatile i16 [[A3_SROA_0_0_A3_SROA_0_0_COPYLOAD1]], ptr [[DST]], align 1
502502
; CHECK-NEXT: [[A3_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 2
@@ -548,26 +548,22 @@ declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias
548548
!15 = !{i64 0, i64 7, !6, i64 7, i64 1, !6}
549549
!16 = !{i64 0, i64 2, !6, i64 4, i64 4, !6, i64 8, i64 1, !6}
550550
;.
551-
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 4, [[META1:![0-9]+]], i64 4, i64 4, [[META1]]}
552-
; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
551+
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 4, [[TBAA1]], i64 4, i64 4, [[TBAA1]]}
552+
; CHECK: [[TBAA1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
553553
; CHECK: [[META2]] = !{!"float", [[META3:![0-9]+]], i64 0}
554554
; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
555555
; CHECK: [[META4]] = !{!"Simple C++ TBAA"}
556-
; CHECK: [[TBAA_STRUCT5]] = !{i64 0, i64 4, [[META1]]}
557-
; CHECK: [[TBAA_STRUCT6]] = !{i64 0, i64 8, [[META7:![0-9]+]], i64 8, i64 4, [[META1]]}
558-
; CHECK: [[META7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
556+
; CHECK: [[TBAA_STRUCT5]] = !{i64 0, i64 4, [[TBAA1]]}
557+
; CHECK: [[TBAA_STRUCT6]] = !{i64 0, i64 8, [[TBAA7]], i64 8, i64 4, [[TBAA1]]}
558+
; CHECK: [[TBAA7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
559559
; CHECK: [[META8]] = !{!"v2f32", [[META3]], i64 0}
560-
; CHECK: [[TBAA_STRUCT9]] = !{i64 0, i64 4, [[META1]], i64 4, i64 8, [[META7]]}
561-
; CHECK: [[TBAA_STRUCT10]] = !{i64 0, i64 8, [[META7]]}
562-
; CHECK: [[TBAA_STRUCT11]] = !{i64 0, i64 8, [[META7]], i64 4, i64 8, [[META1]]}
563-
; CHECK: [[TBAA_STRUCT12]] = !{i64 0, i64 2, [[META1]], i64 2, i64 6, [[META1]]}
564-
; CHECK: [[TBAA_STRUCT13]] = !{i64 0, i64 2, [[META1]]}
565-
; CHECK: [[TBAA_STRUCT14]] = !{i64 0, i64 7, [[META7]], i64 7, i64 1, [[META7]]}
566-
; CHECK: [[TBAA_STRUCT15]] = !{i64 0, i64 1, [[META7]]}
567-
; CHECK: [[TBAA_STRUCT16]] = !{i64 0, i64 2, [[META1]], i64 2, i64 2, [[META1]]}
568-
; CHECK: [[TBAA_STRUCT17]] = !{i64 0, i64 3, [[META1]]}
569-
; CHECK: [[TBAA_STRUCT18]] = !{i64 0, i64 1, [[META1]]}
570-
; CHECK: [[TBAA_STRUCT19]] = !{i64 0, i64 4, [[META7]]}
571-
; CHECK: [[TBAA_STRUCT20]] = !{i64 0, i64 2, [[META7]], i64 4, i64 4, [[META7]], i64 8, i64 1, [[META7]]}
572-
; CHECK: [[TBAA_STRUCT21]] = !{i64 0, i64 4, [[META7]], i64 4, i64 1, [[META7]]}
560+
; CHECK: [[TBAA_STRUCT9]] = !{i64 0, i64 4, [[TBAA1]], i64 4, i64 8, [[TBAA7]]}
561+
; CHECK: [[TBAA_STRUCT10]] = !{i64 0, i64 8, [[TBAA7]], i64 4, i64 8, [[TBAA1]]}
562+
; CHECK: [[TBAA_STRUCT11]] = !{i64 0, i64 2, [[TBAA1]], i64 2, i64 6, [[TBAA1]]}
563+
; CHECK: [[TBAA_STRUCT12]] = !{i64 0, i64 7, [[TBAA7]], i64 7, i64 1, [[TBAA7]]}
564+
; CHECK: [[TBAA_STRUCT13]] = !{i64 0, i64 2, [[TBAA1]], i64 2, i64 2, [[TBAA1]]}
565+
; CHECK: [[TBAA_STRUCT14]] = !{i64 0, i64 3, [[TBAA1]]}
566+
; CHECK: [[TBAA_STRUCT15]] = !{i64 0, i64 4, [[TBAA7]]}
567+
; CHECK: [[TBAA_STRUCT16]] = !{i64 0, i64 2, [[TBAA7]], i64 4, i64 4, [[TBAA7]], i64 8, i64 1, [[TBAA7]]}
568+
; CHECK: [[TBAA_STRUCT17]] = !{i64 0, i64 4, [[TBAA7]], i64 4, i64 1, [[TBAA7]]}
573569
;.

0 commit comments

Comments
 (0)
Please sign in to comment.