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fix true16 usemi
1 parent f536f71 commit 54fa2b0

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2 files changed

+17
-1
lines changed

2 files changed

+17
-1
lines changed

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7835,6 +7835,22 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
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assert(NewDstRC);
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NewDstReg = MRI.createVirtualRegister(NewDstRC);
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MRI.replaceRegWith(DstReg, NewDstReg);
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// Check useMI of NewInstr. If useMI is a true16 instruction,
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// add a lo16 subreg access if needed
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if (ST.useRealTrue16Insts() && 32 == RI.getRegSizeInBits(*NewDstRC)) {
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for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
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E = MRI.use_end();
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I != E; ++I) {
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MachineInstr &UseMI = *I->getParent();
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unsigned UseMIOpcode = UseMI.getOpcode();
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if (AMDGPU::isTrue16Inst(UseMIOpcode) &&
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(16 ==
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RI.getRegSizeInBits(*getOpRegClass(UseMI, I.getOperandNo())))) {
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I->setSubReg(AMDGPU::lo16);
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}
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}
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}
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}
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fixImplicitOperands(*NewInstr);
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// Legalize the operands

llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -699,7 +699,7 @@ define amdgpu_ps half @fneg_fadd_0_f16(half inreg %tmp2, half inreg %tmp6, <4 x
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; GFX11-SAFE-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, s0, v0.l
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; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v1
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; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v0/*Invalid register, operand has 'VS_16' register class*/, s0, vcc_lo
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; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, s0, vcc_lo
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; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-SAFE-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, 0, v0.l
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; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, 0, vcc_lo

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