Skip to content

Commit 5599c78

Browse files
jacquesguanjacquesguan
committed
[RISCV] Add codegen support for Zvfbfmin
1 parent bc8726b commit 5599c78

12 files changed

+535
-33
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 37 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1080,6 +1080,21 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
10801080
}
10811081
}
10821082

1083+
// TODO: Could we merge some code with zvfhmin?
1084+
if (Subtarget.hasVInstructionsBF16()) {
1085+
for (MVT VT : BF16VecVTs) {
1086+
if (!isTypeLegal(VT))
1087+
continue;
1088+
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
1089+
setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
1090+
setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
1091+
ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR},
1092+
VT, Custom);
1093+
setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
1094+
// TODO: Promote to fp32.
1095+
}
1096+
}
1097+
10831098
if (Subtarget.hasVInstructionsF32()) {
10841099
for (MVT VT : F32VecVTs) {
10851100
if (!isTypeLegal(VT))
@@ -1295,6 +1310,17 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
12951310
continue;
12961311
}
12971312

1313+
if (VT.getVectorElementType() == MVT::bf16) {
1314+
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
1315+
setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
1316+
setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
1317+
ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR},
1318+
VT, Custom);
1319+
setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
1320+
// TODO: Promote to fp32.
1321+
continue;
1322+
}
1323+
12981324
// We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
12991325
setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT,
13001326
Custom);
@@ -2549,6 +2575,10 @@ static bool useRVVForFixedLengthVectorVT(MVT VT,
25492575
if (!Subtarget.hasVInstructionsF16Minimal())
25502576
return false;
25512577
break;
2578+
case MVT::bf16:
2579+
if (!Subtarget.hasVInstructionsBF16())
2580+
return false;
2581+
break;
25522582
case MVT::f32:
25532583
if (!Subtarget.hasVInstructionsF32())
25542584
return false;
@@ -2600,6 +2630,7 @@ static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT,
26002630
case MVT::i16:
26012631
case MVT::i32:
26022632
case MVT::i64:
2633+
case MVT::bf16:
26032634
case MVT::f16:
26042635
case MVT::f32:
26052636
case MVT::f64: {
@@ -8086,9 +8117,12 @@ RISCVTargetLowering::lowerVectorFPExtendOrRoundLike(SDValue Op,
80868117
SDValue Src = Op.getOperand(0);
80878118
MVT SrcVT = Src.getSimpleValueType();
80888119

8089-
bool IsDirectExtend = IsExtend && (VT.getVectorElementType() != MVT::f64 ||
8090-
SrcVT.getVectorElementType() != MVT::f16);
8091-
bool IsDirectTrunc = !IsExtend && (VT.getVectorElementType() != MVT::f16 ||
8120+
bool IsDirectExtend =
8121+
IsExtend && (VT.getVectorElementType() != MVT::f64 ||
8122+
(SrcVT.getVectorElementType() != MVT::f16 &&
8123+
SrcVT.getVectorElementType() != MVT::bf16));
8124+
bool IsDirectTrunc = !IsExtend && ((VT.getVectorElementType() != MVT::f16 &&
8125+
VT.getVectorElementType() != MVT::bf16) ||
80928126
SrcVT.getVectorElementType() != MVT::f64);
80938127

80948128
bool IsDirectConv = IsDirectExtend || IsDirectTrunc;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1450,6 +1450,20 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
14501450
fvti.AVL, fvti.Log2SEW, TA_MA)>;
14511451
}
14521452

1453+
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
1454+
defvar fvti = fvtiToFWti.Vti;
1455+
defvar fwti = fvtiToFWti.Wti;
1456+
let Predicates = [HasVInstructionsBF16] in
1457+
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
1458+
(!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX)
1459+
(fvti.Vector (IMPLICIT_DEF)),
1460+
fwti.RegClass:$rs1,
1461+
// Value to indicate no rounding mode change in
1462+
// RISCVInsertReadWriteCSR
1463+
FRM_DYN,
1464+
fvti.AVL, fvti.Log2SEW, TA_MA)>;
1465+
}
1466+
14531467
//===----------------------------------------------------------------------===//
14541468
// Vector Splats
14551469
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2668,6 +2668,20 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
26682668
GPR:$vl, fvti.Log2SEW, TA_MA)>;
26692669
}
26702670

2671+
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
2672+
defvar fvti = fvtiToFWti.Vti;
2673+
defvar fwti = fvtiToFWti.Wti;
2674+
let Predicates = [HasVInstructionsBF16] in
2675+
def : Pat<(fwti.Vector (any_riscv_fpextend_vl
2676+
(fvti.Vector fvti.RegClass:$rs1),
2677+
(fvti.Mask V0),
2678+
VLOpFrag)),
2679+
(!cast<Instruction>("PseudoVFWCVTBF16_F_F_V_"#fvti.LMul.MX#"_MASK")
2680+
(fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
2681+
(fvti.Mask V0),
2682+
GPR:$vl, fvti.Log2SEW, TA_MA)>;
2683+
}
2684+
26712685
// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
26722686
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
26732687
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_x_f_vl, "PseudoVFNCVT_X_F_W">;
@@ -2712,6 +2726,22 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
27122726
}
27132727
}
27142728

2729+
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
2730+
defvar fvti = fvtiToFWti.Vti;
2731+
defvar fwti = fvtiToFWti.Wti;
2732+
let Predicates = [HasVInstructionsBF16] in
2733+
def : Pat<(fvti.Vector (any_riscv_fpround_vl
2734+
(fwti.Vector fwti.RegClass:$rs1),
2735+
(fwti.Mask V0), VLOpFrag)),
2736+
(!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_MASK")
2737+
(fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
2738+
(fwti.Mask V0),
2739+
// Value to indicate no rounding mode change in
2740+
// RISCVInsertReadWriteCSR
2741+
FRM_DYN,
2742+
GPR:$vl, fvti.Log2SEW, TA_MA)>;
2743+
}
2744+
27152745
// 14. Vector Reduction Operations
27162746

27172747
// 14.1. Vector Single-Width Integer Reduction Instructions

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll‎

Lines changed: 54 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
3-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
4-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
5-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck %s
3+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck %s
5+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck %s
66

77
declare <2 x float> @llvm.vp.fpext.v2f32.v2f16(<2 x half>, <2 x i1>, i32)
88

@@ -120,3 +120,53 @@ define <32 x double> @vfpext_v32f32_v32f64(<32 x float> %a, <32 x i1> %m, i32 ze
120120
%v = call <32 x double> @llvm.vp.fpext.v32f64.v32f32(<32 x float> %a, <32 x i1> %m, i32 %vl)
121121
ret <32 x double> %v
122122
}
123+
124+
declare <2 x float> @llvm.vp.fpext.v2f32.v2bf16(<2 x bfloat>, <2 x i1>, i32)
125+
126+
define <2 x float> @vfpext_v2bf16_v2f32(<2 x bfloat> %a, <2 x i1> %m, i32 zeroext %vl) {
127+
; CHECK-LABEL: vfpext_v2bf16_v2f32:
128+
; CHECK: # %bb.0:
129+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
130+
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
131+
; CHECK-NEXT: vmv1r.v v8, v9
132+
; CHECK-NEXT: ret
133+
%v = call <2 x float> @llvm.vp.fpext.v2f32.v2bf16(<2 x bfloat> %a, <2 x i1> %m, i32 %vl)
134+
ret <2 x float> %v
135+
}
136+
137+
define <2 x float> @vfpext_v2bf16_v2f32_unmasked(<2 x bfloat> %a, i32 zeroext %vl) {
138+
; CHECK-LABEL: vfpext_v2bf16_v2f32_unmasked:
139+
; CHECK: # %bb.0:
140+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
141+
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
142+
; CHECK-NEXT: vmv1r.v v8, v9
143+
; CHECK-NEXT: ret
144+
%v = call <2 x float> @llvm.vp.fpext.v2f32.v2bf16(<2 x bfloat> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl)
145+
ret <2 x float> %v
146+
}
147+
148+
declare <2 x double> @llvm.vp.fpext.v2f64.v2bf16(<2 x bfloat>, <2 x i1>, i32)
149+
150+
define <2 x double> @vfpext_v2bf16_v2f64(<2 x bfloat> %a, <2 x i1> %m, i32 zeroext %vl) {
151+
; CHECK-LABEL: vfpext_v2bf16_v2f64:
152+
; CHECK: # %bb.0:
153+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
154+
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
155+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
156+
; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t
157+
; CHECK-NEXT: ret
158+
%v = call <2 x double> @llvm.vp.fpext.v2f64.v2bf16(<2 x bfloat> %a, <2 x i1> %m, i32 %vl)
159+
ret <2 x double> %v
160+
}
161+
162+
define <2 x double> @vfpext_v2bf16_v2f64_unmasked(<2 x bfloat> %a, i32 zeroext %vl) {
163+
; CHECK-LABEL: vfpext_v2bf16_v2f64_unmasked:
164+
; CHECK: # %bb.0:
165+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
166+
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
167+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
168+
; CHECK-NEXT: vfwcvt.f.f.v v8, v9
169+
; CHECK-NEXT: ret
170+
%v = call <2 x double> @llvm.vp.fpext.v2f64.v2bf16(<2 x bfloat> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl)
171+
ret <2 x double> %v
172+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll‎

Lines changed: 54 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
3-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
4-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
5-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck %s
3+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck %s
5+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck %s
66

77

88
declare <2 x half> @llvm.vp.fptrunc.v2f16.v2f32(<2 x float>, <2 x i1>, i32)
@@ -122,3 +122,53 @@ define <32 x float> @vfptrunc_v32f32_v32f64(<32 x double> %a, <32 x i1> %m, i32
122122
%v = call <32 x float> @llvm.vp.fptrunc.v32f64.v32f32(<32 x double> %a, <32 x i1> %m, i32 %vl)
123123
ret <32 x float> %v
124124
}
125+
126+
declare <2 x bfloat> @llvm.vp.fptrunc.v2bf16.v2f32(<2 x float>, <2 x i1>, i32)
127+
128+
define <2 x bfloat> @vfptrunc_v2bf16_v2f32(<2 x float> %a, <2 x i1> %m, i32 zeroext %vl) {
129+
; CHECK-LABEL: vfptrunc_v2bf16_v2f32:
130+
; CHECK: # %bb.0:
131+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
132+
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8, v0.t
133+
; CHECK-NEXT: vmv1r.v v8, v9
134+
; CHECK-NEXT: ret
135+
%v = call <2 x bfloat> @llvm.vp.fptrunc.v2bf16.v2f32(<2 x float> %a, <2 x i1> %m, i32 %vl)
136+
ret <2 x bfloat> %v
137+
}
138+
139+
define <2 x bfloat> @vfptrunc_v2bf16_v2f32_unmasked(<2 x float> %a, i32 zeroext %vl) {
140+
; CHECK-LABEL: vfptrunc_v2bf16_v2f32_unmasked:
141+
; CHECK: # %bb.0:
142+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
143+
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8
144+
; CHECK-NEXT: vmv1r.v v8, v9
145+
; CHECK-NEXT: ret
146+
%v = call <2 x bfloat> @llvm.vp.fptrunc.v2bf16.v2f32(<2 x float> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl)
147+
ret <2 x bfloat> %v
148+
}
149+
150+
declare <2 x bfloat> @llvm.vp.fptrunc.v2bf16.v2f64(<2 x double>, <2 x i1>, i32)
151+
152+
define <2 x bfloat> @vfptrunc_v2bf16_v2f64(<2 x double> %a, <2 x i1> %m, i32 zeroext %vl) {
153+
; CHECK-LABEL: vfptrunc_v2bf16_v2f64:
154+
; CHECK: # %bb.0:
155+
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
156+
; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8, v0.t
157+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
158+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
159+
; CHECK-NEXT: ret
160+
%v = call <2 x bfloat> @llvm.vp.fptrunc.v2bf16.v2f64(<2 x double> %a, <2 x i1> %m, i32 %vl)
161+
ret <2 x bfloat> %v
162+
}
163+
164+
define <2 x bfloat> @vfptrunc_v2bf16_v2f64_unmasked(<2 x double> %a, i32 zeroext %vl) {
165+
; CHECK-LABEL: vfptrunc_v2bf16_v2f64_unmasked:
166+
; CHECK: # %bb.0:
167+
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
168+
; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
169+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
170+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
171+
; CHECK-NEXT: ret
172+
%v = call <2 x bfloat> @llvm.vp.fptrunc.v2bf16.v2f64(<2 x double> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl)
173+
ret <2 x bfloat> %v
174+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll‎

Lines changed: 20 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2-
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
3-
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
3+
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
44

55
define void @v2i8(ptr %p, ptr %q) {
66
; CHECK-LABEL: v2i8:
@@ -301,3 +301,21 @@ define void @v2i8_volatile_store(ptr %p, ptr %q) {
301301
store volatile <2 x i8> %v, ptr %q
302302
ret void
303303
}
304+
305+
define void @v4bf16(ptr %p, ptr %q) {
306+
; RV32-LABEL: v4bf16:
307+
; RV32: # %bb.0:
308+
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
309+
; RV32-NEXT: vle16.v v8, (a0)
310+
; RV32-NEXT: vse16.v v8, (a1)
311+
; RV32-NEXT: ret
312+
;
313+
; RV64-LABEL: v4bf16:
314+
; RV64: # %bb.0:
315+
; RV64-NEXT: ld a0, 0(a0)
316+
; RV64-NEXT: sd a0, 0(a1)
317+
; RV64-NEXT: ret
318+
%v = load <4 x bfloat>, ptr %p
319+
store <4 x bfloat> %v, ptr %q
320+
ret void
321+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2-
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
3-
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
3+
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
44

55
define <5 x i8> @load_v5i8(ptr %p) {
66
; CHECK-LABEL: load_v5i8:
@@ -181,3 +181,13 @@ define <16 x i64> @exact_vlen_i64_m8(ptr %p) vscale_range(2,2) {
181181
%v = load <16 x i64>, ptr %p
182182
ret <16 x i64> %v
183183
}
184+
185+
define <6 x bfloat> @load_v6bf16(ptr %p) {
186+
; CHECK-LABEL: load_v6bf16:
187+
; CHECK: # %bb.0:
188+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
189+
; CHECK-NEXT: vle16.v v8, (a0)
190+
; CHECK-NEXT: ret
191+
%x = load <6 x bfloat>, ptr %p
192+
ret <6 x bfloat> %x
193+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2-
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
3-
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
3+
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
44

55
define void @store_v5i8(ptr %p, <5 x i8> %v) {
66
; CHECK-LABEL: store_v5i8:
@@ -294,6 +294,16 @@ define void @exact_vlen_i64_m8(ptr %p) vscale_range(2,2) {
294294
ret void
295295
}
296296

297+
define void @store_v8bf16(ptr %p, <8 x bfloat> %v) {
298+
; CHECK-LABEL: store_v8bf16:
299+
; CHECK: # %bb.0:
300+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
301+
; CHECK-NEXT: vse16.v v8, (a0)
302+
; CHECK-NEXT: ret
303+
store <8 x bfloat> %v, ptr %p
304+
ret void
305+
}
306+
297307
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
298308
; RV32: {{.*}}
299309
; RV64: {{.*}}

0 commit comments

Comments
 (0)