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[AMDGPU][AsmParser][NFC] Simplify instruction operand definitions.
This addresses the trivial cases that only require removing the operand classes and renaming related entities. Part of <#62629>. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D153965
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-100
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6 files changed

+35
-100
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -864,7 +864,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
864864

865865
bool isSWaitCnt() const;
866866
bool isDepCtr() const;
867-
bool isSDelayAlu() const;
867+
bool isSDelayALU() const;
868868
bool isHwreg() const;
869869
bool isSendMsg() const;
870870
bool isSwizzle() const;
@@ -1602,14 +1602,14 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
16021602
void cvtExp(MCInst &Inst, const OperandVector &Operands);
16031603

16041604
bool parseCnt(int64_t &IntVal);
1605-
OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
1605+
OperandMatchResultTy parseSWaitCnt(OperandVector &Operands);
16061606

16071607
bool parseDepCtr(int64_t &IntVal, unsigned &Mask);
16081608
void depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName);
1609-
OperandMatchResultTy parseDepCtrOps(OperandVector &Operands);
1609+
OperandMatchResultTy parseDepCtr(OperandVector &Operands);
16101610

16111611
bool parseDelay(int64_t &Delay);
1612-
OperandMatchResultTy parseSDelayAluOps(OperandVector &Operands);
1612+
OperandMatchResultTy parseSDelayALU(OperandVector &Operands);
16131613

16141614
OperandMatchResultTy parseHwreg(OperandVector &Operands);
16151615

@@ -1723,7 +1723,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17231723
unsigned MCK);
17241724

17251725
OperandMatchResultTy parseExpTgt(OperandVector &Operands);
1726-
OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
1726+
OperandMatchResultTy parseSendMsg(OperandVector &Operands);
17271727
OperandMatchResultTy parseInterpSlot(OperandVector &Operands);
17281728
OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
17291729
OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
@@ -1738,7 +1738,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17381738
const unsigned MinVal,
17391739
const unsigned MaxVal,
17401740
const StringRef ErrMsg);
1741-
OperandMatchResultTy parseSwizzleOp(OperandVector &Operands);
1741+
OperandMatchResultTy parseSwizzle(OperandVector &Operands);
17421742
bool parseSwizzleOffset(int64_t &Imm);
17431743
bool parseSwizzleMacro(int64_t &Imm);
17441744
bool parseSwizzleQuadPerm(int64_t &Imm);
@@ -6588,8 +6588,7 @@ bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
65886588
return true;
65896589
}
65906590

6591-
OperandMatchResultTy
6592-
AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
6591+
OperandMatchResultTy AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {
65936592
AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
65946593
int64_t Waitcnt = getWaitcntBitMask(ISA);
65956594
SMLoc S = getLoc();
@@ -6670,8 +6669,7 @@ bool AMDGPUAsmParser::parseDelay(int64_t &Delay) {
66706669
return true;
66716670
}
66726671

6673-
OperandMatchResultTy
6674-
AMDGPUAsmParser::parseSDelayAluOps(OperandVector &Operands) {
6672+
OperandMatchResultTy AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {
66756673
int64_t Delay = 0;
66766674
SMLoc S = getLoc();
66776675

@@ -6694,7 +6692,7 @@ AMDGPUOperand::isSWaitCnt() const {
66946692
return isImm();
66956693
}
66966694

6697-
bool AMDGPUOperand::isSDelayAlu() const { return isImm(); }
6695+
bool AMDGPUOperand::isSDelayALU() const { return isImm(); }
66986696

66996697
//===----------------------------------------------------------------------===//
67006698
// DepCtr
@@ -6758,7 +6756,7 @@ bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {
67586756
return true;
67596757
}
67606758

6761-
OperandMatchResultTy AMDGPUAsmParser::parseDepCtrOps(OperandVector &Operands) {
6759+
OperandMatchResultTy AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {
67626760
using namespace llvm::AMDGPU::DepCtr;
67636761

67646762
int64_t DepCtr = getDefaultDepCtrEncoding(getSTI());
@@ -6972,8 +6970,7 @@ AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg,
69726970
return true;
69736971
}
69746972

6975-
OperandMatchResultTy
6976-
AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {
6973+
OperandMatchResultTy AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {
69776974
using namespace llvm::AMDGPU::SendMsg;
69786975

69796976
int64_t ImmVal = 0;
@@ -7567,8 +7564,7 @@ AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
75677564
return false;
75687565
}
75697566

7570-
OperandMatchResultTy
7571-
AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) {
7567+
OperandMatchResultTy AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {
75727568
SMLoc S = getLoc();
75737569
int64_t Imm = 0;
75747570

‎llvm/lib/Target/AMDGPU/DSInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -631,7 +631,7 @@ def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
631631
} // End SubtargetPredicate = HasDsSrc2Insts
632632

633633
let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
634-
def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
634+
def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, Swizzle>;
635635
}
636636

637637
let mayStore = 0 in {

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1277,9 +1277,9 @@ void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
12771277
O << '.' << "xyzw"[Chan & 0x3];
12781278
}
12791279

1280-
void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1281-
const MCSubtargetInfo &STI,
1282-
raw_ostream &O) {
1280+
void AMDGPUInstPrinter::printGPRIdxMode(const MCInst *MI, unsigned OpNo,
1281+
const MCSubtargetInfo &STI,
1282+
raw_ostream &O) {
12831283
using namespace llvm::AMDGPU::VGPRIndexMode;
12841284
unsigned Val = MI->getOperand(OpNo).getImm();
12851285

@@ -1486,7 +1486,7 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
14861486
}
14871487
}
14881488

1489-
void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1489+
void AMDGPUInstPrinter::printSWaitCnt(const MCInst *MI, unsigned OpNo,
14901490
const MCSubtargetInfo &STI,
14911491
raw_ostream &O) {
14921492
AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
@@ -1548,7 +1548,7 @@ void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
15481548
}
15491549
}
15501550

1551-
void AMDGPUInstPrinter::printDelayFlag(const MCInst *MI, unsigned OpNo,
1551+
void AMDGPUInstPrinter::printSDelayALU(const MCInst *MI, unsigned OpNo,
15521552
const MCSubtargetInfo &STI,
15531553
raw_ostream &O) {
15541554
const char *BadInstId = "/* invalid instid value */";

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -165,8 +165,8 @@ class AMDGPUInstPrinter : public MCInstPrinter {
165165
void printInterpAttrChan(const MCInst *MI, unsigned OpNo,
166166
const MCSubtargetInfo &STI, raw_ostream &O);
167167

168-
void printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
169-
const MCSubtargetInfo &STI, raw_ostream &O);
168+
void printGPRIdxMode(const MCInst *MI, unsigned OpNo,
169+
const MCSubtargetInfo &STI, raw_ostream &O);
170170
void printMemOperand(const MCInst *MI, unsigned OpNo,
171171
const MCSubtargetInfo &STI, raw_ostream &O);
172172
void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
@@ -240,11 +240,11 @@ class AMDGPUInstPrinter : public MCInstPrinter {
240240
raw_ostream &O);
241241
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
242242
raw_ostream &O);
243-
void printWaitFlag(const MCInst *MI, unsigned OpNo,
243+
void printSWaitCnt(const MCInst *MI, unsigned OpNo,
244244
const MCSubtargetInfo &STI, raw_ostream &O);
245245
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
246246
raw_ostream &O);
247-
void printDelayFlag(const MCInst *MI, unsigned OpNo,
247+
void printSDelayALU(const MCInst *MI, unsigned OpNo,
248248
const MCSubtargetInfo &STI, raw_ostream &O);
249249
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
250250
raw_ostream &O);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 5 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -943,72 +943,22 @@ def InterpAttr : CustomOperand<i32>;
943943

944944
def InterpAttrChan : ImmOperand<i32>;
945945

946-
def SendMsgMatchClass : AsmOperandClass {
947-
let Name = "SendMsg";
948-
let PredicateMethod = "isSendMsg";
949-
let ParserMethod = "parseSendMsgOp";
950-
let RenderMethod = "addImmOperands";
951-
}
952-
953-
def SwizzleMatchClass : AsmOperandClass {
954-
let Name = "Swizzle";
955-
let PredicateMethod = "isSwizzle";
956-
let ParserMethod = "parseSwizzleOp";
957-
let RenderMethod = "addImmOperands";
958-
let IsOptional = 1;
959-
}
960-
961-
def SWaitMatchClass : AsmOperandClass {
962-
let Name = "SWaitCnt";
963-
let RenderMethod = "addImmOperands";
964-
let ParserMethod = "parseSWaitCntOps";
965-
}
966-
967-
def DepCtrMatchClass : AsmOperandClass {
968-
let Name = "DepCtr";
969-
let RenderMethod = "addImmOperands";
970-
let ParserMethod = "parseDepCtrOps";
971-
}
972-
973-
def SDelayMatchClass : AsmOperandClass {
974-
let Name = "SDelayAlu";
975-
let RenderMethod = "addImmOperands";
976-
let ParserMethod = "parseSDelayAluOps";
977-
}
978-
979946
def VReg32OrOffClass : AsmOperandClass {
980947
let Name = "VReg32OrOff";
981948
let ParserMethod = "parseVReg32OrOff";
982949
}
983950

984-
let OperandType = "OPERAND_IMMEDIATE" in {
985-
def SendMsgImm : Operand<i32> {
986-
let PrintMethod = "printSendMsg";
987-
let ParserMatchClass = SendMsgMatchClass;
988-
}
951+
def SendMsg : CustomOperand<i32>;
989952

990-
def SwizzleImm : Operand<i16> {
991-
let PrintMethod = "printSwizzle";
992-
let ParserMatchClass = SwizzleMatchClass;
993-
}
953+
def Swizzle : CustomOperand<i16, 1>;
994954

995955
def Endpgm : CustomOperand<i16, 1>;
996956

997-
def WAIT_FLAG : Operand <i32> {
998-
let ParserMatchClass = SWaitMatchClass;
999-
let PrintMethod = "printWaitFlag";
1000-
}
957+
def SWaitCnt : CustomOperand<i32>;
1001958

1002-
def DepCtrImm : Operand <i32> {
1003-
let ParserMatchClass = DepCtrMatchClass;
1004-
let PrintMethod = "printDepCtr";
1005-
}
959+
def DepCtr : CustomOperand<i32>;
1006960

1007-
def DELAY_FLAG : Operand <i32> {
1008-
let ParserMatchClass = SDelayMatchClass;
1009-
let PrintMethod = "printDelayFlag";
1010-
}
1011-
} // End OperandType = "OPERAND_IMMEDIATE"
961+
def SDelayALU : CustomOperand<i32>;
1012962

1013963
include "SIInstrFormats.td"
1014964
include "VIInstrFormats.td"

‎llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 8 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -6,18 +6,7 @@
66
//
77
//===----------------------------------------------------------------------===//
88

9-
def GPRIdxModeMatchClass : AsmOperandClass {
10-
let Name = "GPRIdxMode";
11-
let PredicateMethod = "isGPRIdxMode";
12-
let ParserMethod = "parseGPRIdxMode";
13-
let RenderMethod = "addImmOperands";
14-
}
15-
16-
def GPRIdxMode : Operand<i32> {
17-
let PrintMethod = "printVGPRIndexMode";
18-
let ParserMatchClass = GPRIdxModeMatchClass;
19-
let OperandType = "OPERAND_IMMEDIATE";
20-
}
9+
def GPRIdxMode : CustomOperand<i32>;
2110

2211
class SOP_Pseudo<string opName, dag outs, dag ins, string asmOps,
2312
list<dag> pattern=[]> :
@@ -402,11 +391,11 @@ let SubtargetPredicate = isGFX11Plus in {
402391
// For s_sendmsg_rtn_* the src0 field encodes the message type directly; it
403392
// is not an SGPR number.
404393
def S_SENDMSG_RTN_B32 : SOP1_Pseudo<
405-
"s_sendmsg_rtn_b32", (outs SReg_32:$sdst), (ins SendMsgImm:$src0),
394+
"s_sendmsg_rtn_b32", (outs SReg_32:$sdst), (ins SendMsg:$src0),
406395
"$sdst, $src0", [(set i32:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))]
407396
>;
408397
def S_SENDMSG_RTN_B64 : SOP1_Pseudo<
409-
"s_sendmsg_rtn_b64", (outs SReg_64:$sdst), (ins SendMsgImm:$src0),
398+
"s_sendmsg_rtn_b64", (outs SReg_64:$sdst), (ins SendMsg:$src0),
410399
"$sdst, $src0", [(set i64:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))]
411400
>;
412401
}
@@ -1284,7 +1273,7 @@ def S_WAKEUP : SOPP_Pseudo <"s_wakeup", (ins) > {
12841273
}
12851274

12861275
let hasSideEffects = 1 in
1287-
def S_WAITCNT : SOPP_Pseudo <"s_waitcnt" , (ins WAIT_FLAG:$simm16), "$simm16",
1276+
def S_WAITCNT : SOPP_Pseudo <"s_waitcnt" , (ins SWaitCnt:$simm16), "$simm16",
12881277
[(int_amdgcn_s_waitcnt timm:$simm16)]>;
12891278
def S_SETHALT : SOPP_Pseudo <"s_sethalt" , (ins i32imm:$simm16), "$simm16",
12901279
[(int_amdgcn_s_sethalt timm:$simm16)]>;
@@ -1305,12 +1294,12 @@ def S_SETPRIO : SOPP_Pseudo <"s_setprio", (ins i16imm:$simm16), "$simm16",
13051294
}
13061295

13071296
let Uses = [EXEC, M0] in {
1308-
def S_SENDMSG : SOPP_Pseudo <"s_sendmsg" , (ins SendMsgImm:$simm16), "$simm16",
1297+
def S_SENDMSG : SOPP_Pseudo <"s_sendmsg" , (ins SendMsg:$simm16), "$simm16",
13091298
[(int_amdgcn_s_sendmsg (i32 timm:$simm16), M0)]> {
13101299
let hasSideEffects = 1;
13111300
}
13121301

1313-
def S_SENDMSGHALT : SOPP_Pseudo <"s_sendmsghalt" , (ins SendMsgImm:$simm16), "$simm16",
1302+
def S_SENDMSGHALT : SOPP_Pseudo <"s_sendmsghalt" , (ins SendMsg:$simm16), "$simm16",
13141303
[(int_amdgcn_s_sendmsghalt (i32 timm:$simm16), M0)]> {
13151304
let hasSideEffects = 1;
13161305
}
@@ -1367,7 +1356,7 @@ let SubtargetPredicate = isGFX10Plus in {
13671356
let fixed_imm = 1;
13681357
}
13691358
def S_WAITCNT_DEPCTR :
1370-
SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtrImm:$simm16), "$simm16">;
1359+
SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtr:$simm16), "$simm16">;
13711360

13721361
let hasSideEffects = 0, Uses = [MODE], Defs = [MODE] in {
13731362
def S_ROUND_MODE :
@@ -1386,7 +1375,7 @@ let SubtargetPredicate = isGFX11Plus in {
13861375
"$simm16"> {
13871376
let hasSideEffects = 1;
13881377
}
1389-
def S_DELAY_ALU : SOPP_Pseudo<"s_delay_alu", (ins DELAY_FLAG:$simm16),
1378+
def S_DELAY_ALU : SOPP_Pseudo<"s_delay_alu", (ins SDelayALU:$simm16),
13901379
"$simm16">;
13911380
} // End SubtargetPredicate = isGFX11Plus
13921381

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