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[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
True16 codegen for FPtoi1. It seems tablegen figured out the pattern even without this pat in place, and the fptoui/fptosi.ll already got the right transformation. Aditionally updated the mir file and split it to pre-gfx11 and post-gfx11.
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‎llvm/lib/Target/AMDGPU/SIInstructions.td

+9-4
Original file line numberDiff line numberDiff line change
@@ -2703,15 +2703,20 @@ class FPToI1Pat<Instruction Inst, int KOne, ValueType kone_type, ValueType vt, S
27032703
(i1 (Inst 0, (kone_type KOne), $src0_modifiers, $src0, DSTCLAMP.NONE))
27042704
>;
27052705

2706-
let OtherPredicates = [NotHasTrue16BitInsts] in {
2706+
let True16Predicate = NotHasTrue16BitInsts in {
27072707
def : FPToI1Pat<V_CMP_EQ_F16_e64, CONST.FP16_ONE, i16, f16, fp_to_uint>;
27082708
def : FPToI1Pat<V_CMP_EQ_F16_e64, CONST.FP16_NEG_ONE, i16, f16, fp_to_sint>;
2709-
} // end OtherPredicates = [NotHasTrue16BitInsts]
2709+
} // end True16Predicate = NotHasTrue16BitInsts
2710+
2711+
let True16Predicate = UseRealTrue16Insts in {
2712+
def : FPToI1Pat<V_CMP_EQ_F16_t16_e64, CONST.FP16_ONE, i16, f16, fp_to_uint>;
2713+
def : FPToI1Pat<V_CMP_EQ_F16_t16_e64, CONST.FP16_NEG_ONE, i16, f16, fp_to_sint>;
2714+
} // end True16Predicate = UseRealTrue16BitInsts
27102715

2711-
let OtherPredicates = [HasTrue16BitInsts] in {
2716+
let True16Predicate = UseFakeTrue16Insts in {
27122717
def : FPToI1Pat<V_CMP_EQ_F16_fake16_e64, CONST.FP16_ONE, i16, f16, fp_to_uint>;
27132718
def : FPToI1Pat<V_CMP_EQ_F16_fake16_e64, CONST.FP16_NEG_ONE, i16, f16, fp_to_sint>;
2714-
} // end OtherPredicates = [HasTrue16BitInsts]
2719+
} // end True16Predicate = UseFakeTrue16BitInsts
27152720

27162721
def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_ONE, i32, f32, fp_to_uint>;
27172722
def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_NEG_ONE, i32, f32, fp_to_sint>;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir

+374
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,374 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -mattr=-real-true16 -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX11 %s
3+
4+
---
5+
name: fcmp_false_s16_vv
6+
legalized: true
7+
regBankSelected: true
8+
9+
body: |
10+
bb.0:
11+
liveins: $vgpr0, $vgpr1
12+
; GFX11-LABEL: name: fcmp_false_s16_vv
13+
; GFX11: liveins: $vgpr0, $vgpr1
14+
; GFX11-NEXT: {{ $}}
15+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
16+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
17+
; GFX11-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
18+
; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
19+
; GFX11-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[TRUNC]](s16), [[TRUNC1]]
20+
; GFX11-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
21+
%0:vgpr(s32) = COPY $vgpr0
22+
%1:vgpr(s32) = COPY $vgpr1
23+
%2:vgpr(s16) = G_TRUNC %0
24+
%3:vgpr(s16) = G_TRUNC %1
25+
%4:vcc(s1) = G_FCMP floatpred(false), %2, %3
26+
S_ENDPGM 0, implicit %4
27+
...
28+
29+
---
30+
name: fcmp_oeq_s16_vv
31+
legalized: true
32+
regBankSelected: true
33+
34+
body: |
35+
bb.0:
36+
liveins: $vgpr0, $vgpr1
37+
; GFX11-LABEL: name: fcmp_oeq_s16_vv
38+
; GFX11: liveins: $vgpr0, $vgpr1
39+
; GFX11-NEXT: {{ $}}
40+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
41+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
42+
; GFX11-NEXT: [[V_CMP_EQ_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
43+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_fake16_e64_]]
44+
%0:vgpr(s32) = COPY $vgpr0
45+
%1:vgpr(s32) = COPY $vgpr1
46+
%2:vgpr(s16) = G_TRUNC %0
47+
%3:vgpr(s16) = G_TRUNC %1
48+
%4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3
49+
S_ENDPGM 0, implicit %4
50+
...
51+
52+
---
53+
name: fcmp_ogt_s16_vv
54+
legalized: true
55+
regBankSelected: true
56+
57+
body: |
58+
bb.0:
59+
liveins: $vgpr0, $vgpr1
60+
; GFX11-LABEL: name: fcmp_ogt_s16_vv
61+
; GFX11: liveins: $vgpr0, $vgpr1
62+
; GFX11-NEXT: {{ $}}
63+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
64+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
65+
; GFX11-NEXT: [[V_CMP_GT_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_GT_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
66+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_GT_F16_fake16_e64_]]
67+
%0:vgpr(s32) = COPY $vgpr0
68+
%1:vgpr(s32) = COPY $vgpr1
69+
%2:vgpr(s16) = G_TRUNC %0
70+
%3:vgpr(s16) = G_TRUNC %1
71+
%4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3
72+
S_ENDPGM 0, implicit %4
73+
...
74+
75+
---
76+
name: fcmp_oge_s16_vv
77+
legalized: true
78+
regBankSelected: true
79+
80+
body: |
81+
bb.0:
82+
liveins: $vgpr0, $vgpr1
83+
; GFX11-LABEL: name: fcmp_oge_s16_vv
84+
; GFX11: liveins: $vgpr0, $vgpr1
85+
; GFX11-NEXT: {{ $}}
86+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
87+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
88+
; GFX11-NEXT: [[V_CMP_GE_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_GE_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
89+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_GE_F16_fake16_e64_]]
90+
%0:vgpr(s32) = COPY $vgpr0
91+
%1:vgpr(s32) = COPY $vgpr1
92+
%2:vgpr(s16) = G_TRUNC %0
93+
%3:vgpr(s16) = G_TRUNC %1
94+
%4:vcc(s1) = G_FCMP floatpred(oge), %2, %3
95+
S_ENDPGM 0, implicit %4
96+
...
97+
98+
---
99+
name: fcmp_olt_s16_vv
100+
legalized: true
101+
regBankSelected: true
102+
103+
body: |
104+
bb.0:
105+
liveins: $vgpr0, $vgpr1
106+
; GFX11-LABEL: name: fcmp_olt_s16_vv
107+
; GFX11: liveins: $vgpr0, $vgpr1
108+
; GFX11-NEXT: {{ $}}
109+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
110+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
111+
; GFX11-NEXT: [[V_CMP_LT_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_LT_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
112+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_LT_F16_fake16_e64_]]
113+
%0:vgpr(s32) = COPY $vgpr0
114+
%1:vgpr(s32) = COPY $vgpr1
115+
%2:vgpr(s16) = G_TRUNC %0
116+
%3:vgpr(s16) = G_TRUNC %1
117+
%4:vcc(s1) = G_FCMP floatpred(olt), %2, %3
118+
S_ENDPGM 0, implicit %4
119+
...
120+
121+
---
122+
name: fcmp_ole_s16_vv
123+
legalized: true
124+
regBankSelected: true
125+
126+
body: |
127+
bb.0:
128+
liveins: $vgpr0, $vgpr1
129+
; GFX11-LABEL: name: fcmp_ole_s16_vv
130+
; GFX11: liveins: $vgpr0, $vgpr1
131+
; GFX11-NEXT: {{ $}}
132+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
133+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
134+
; GFX11-NEXT: [[V_CMP_LE_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_LE_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
135+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_LE_F16_fake16_e64_]]
136+
%0:vgpr(s32) = COPY $vgpr0
137+
%1:vgpr(s32) = COPY $vgpr1
138+
%2:vgpr(s16) = G_TRUNC %0
139+
%3:vgpr(s16) = G_TRUNC %1
140+
%4:vcc(s1) = G_FCMP floatpred(ole), %2, %3
141+
S_ENDPGM 0, implicit %4
142+
...
143+
---
144+
name: fcmp_one_s16_vv
145+
legalized: true
146+
regBankSelected: true
147+
148+
body: |
149+
bb.0:
150+
liveins: $vgpr0, $vgpr1
151+
; GFX11-LABEL: name: fcmp_one_s16_vv
152+
; GFX11: liveins: $vgpr0, $vgpr1
153+
; GFX11-NEXT: {{ $}}
154+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
155+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
156+
; GFX11-NEXT: [[V_CMP_LG_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_LG_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
157+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_LG_F16_fake16_e64_]]
158+
%0:vgpr(s32) = COPY $vgpr0
159+
%1:vgpr(s32) = COPY $vgpr1
160+
%2:vgpr(s16) = G_TRUNC %0
161+
%3:vgpr(s16) = G_TRUNC %1
162+
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3
163+
S_ENDPGM 0, implicit %4
164+
...
165+
166+
---
167+
name: fcmp_ord_s16_vv
168+
legalized: true
169+
regBankSelected: true
170+
171+
body: |
172+
bb.0:
173+
liveins: $vgpr0, $vgpr1
174+
; GFX11-LABEL: name: fcmp_ord_s16_vv
175+
; GFX11: liveins: $vgpr0, $vgpr1
176+
; GFX11-NEXT: {{ $}}
177+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
178+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
179+
; GFX11-NEXT: [[V_CMP_LG_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_LG_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
180+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_LG_F16_fake16_e64_]]
181+
%0:vgpr(s32) = COPY $vgpr0
182+
%1:vgpr(s32) = COPY $vgpr1
183+
%2:vgpr(s16) = G_TRUNC %0
184+
%3:vgpr(s16) = G_TRUNC %1
185+
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3
186+
S_ENDPGM 0, implicit %4
187+
...
188+
189+
---
190+
name: fcmp_uno_s16_vv
191+
legalized: true
192+
regBankSelected: true
193+
194+
body: |
195+
bb.0:
196+
liveins: $vgpr0, $vgpr1
197+
; GFX11-LABEL: name: fcmp_uno_s16_vv
198+
; GFX11: liveins: $vgpr0, $vgpr1
199+
; GFX11-NEXT: {{ $}}
200+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
201+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
202+
; GFX11-NEXT: [[V_CMP_U_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_U_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
203+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_U_F16_fake16_e64_]]
204+
%0:vgpr(s32) = COPY $vgpr0
205+
%1:vgpr(s32) = COPY $vgpr1
206+
%2:vgpr(s16) = G_TRUNC %0
207+
%3:vgpr(s16) = G_TRUNC %1
208+
%4:vcc(s1) = G_FCMP floatpred(uno), %2, %3
209+
S_ENDPGM 0, implicit %4
210+
...
211+
212+
---
213+
name: fcmp_ueq_s16_vv
214+
legalized: true
215+
regBankSelected: true
216+
217+
body: |
218+
bb.0:
219+
liveins: $vgpr0, $vgpr1
220+
; GFX11-LABEL: name: fcmp_ueq_s16_vv
221+
; GFX11: liveins: $vgpr0, $vgpr1
222+
; GFX11-NEXT: {{ $}}
223+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
224+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
225+
; GFX11-NEXT: [[V_CMP_NLG_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_NLG_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
226+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_fake16_e64_]]
227+
%0:vgpr(s32) = COPY $vgpr0
228+
%1:vgpr(s32) = COPY $vgpr1
229+
%2:vgpr(s16) = G_TRUNC %0
230+
%3:vgpr(s16) = G_TRUNC %1
231+
%4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3
232+
S_ENDPGM 0, implicit %4
233+
...
234+
235+
---
236+
name: fcmp_ugt_s16_vv
237+
legalized: true
238+
regBankSelected: true
239+
240+
body: |
241+
bb.0:
242+
liveins: $vgpr0, $vgpr1
243+
; GFX11-LABEL: name: fcmp_ugt_s16_vv
244+
; GFX11: liveins: $vgpr0, $vgpr1
245+
; GFX11-NEXT: {{ $}}
246+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
247+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
248+
; GFX11-NEXT: [[V_CMP_NLE_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_NLE_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
249+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_fake16_e64_]]
250+
%0:vgpr(s32) = COPY $vgpr0
251+
%1:vgpr(s32) = COPY $vgpr1
252+
%2:vgpr(s16) = G_TRUNC %0
253+
%3:vgpr(s16) = G_TRUNC %1
254+
%4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3
255+
S_ENDPGM 0, implicit %4
256+
...
257+
258+
---
259+
name: fcmp_uge_s16_vv
260+
legalized: true
261+
regBankSelected: true
262+
263+
body: |
264+
bb.0:
265+
liveins: $vgpr0, $vgpr1
266+
; GFX11-LABEL: name: fcmp_uge_s16_vv
267+
; GFX11: liveins: $vgpr0, $vgpr1
268+
; GFX11-NEXT: {{ $}}
269+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
270+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
271+
; GFX11-NEXT: [[V_CMP_NLT_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_NLT_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
272+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_fake16_e64_]]
273+
%0:vgpr(s32) = COPY $vgpr0
274+
%1:vgpr(s32) = COPY $vgpr1
275+
%2:vgpr(s16) = G_TRUNC %0
276+
%3:vgpr(s16) = G_TRUNC %1
277+
%4:vcc(s1) = G_FCMP floatpred(uge), %2, %3
278+
S_ENDPGM 0, implicit %4
279+
...
280+
281+
---
282+
name: fcmp_ult_s16_vv
283+
legalized: true
284+
regBankSelected: true
285+
286+
body: |
287+
bb.0:
288+
liveins: $vgpr0, $vgpr1
289+
; GFX11-LABEL: name: fcmp_ult_s16_vv
290+
; GFX11: liveins: $vgpr0, $vgpr1
291+
; GFX11-NEXT: {{ $}}
292+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
293+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
294+
; GFX11-NEXT: [[V_CMP_NGE_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_NGE_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
295+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_fake16_e64_]]
296+
%0:vgpr(s32) = COPY $vgpr0
297+
%1:vgpr(s32) = COPY $vgpr1
298+
%2:vgpr(s16) = G_TRUNC %0
299+
%3:vgpr(s16) = G_TRUNC %1
300+
%4:vcc(s1) = G_FCMP floatpred(ult), %2, %3
301+
S_ENDPGM 0, implicit %4
302+
...
303+
304+
---
305+
name: fcmp_ule_s16_vv
306+
legalized: true
307+
regBankSelected: true
308+
309+
body: |
310+
bb.0:
311+
liveins: $vgpr0, $vgpr1
312+
; GFX11-LABEL: name: fcmp_ule_s16_vv
313+
; GFX11: liveins: $vgpr0, $vgpr1
314+
; GFX11-NEXT: {{ $}}
315+
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
316+
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
317+
; GFX11-NEXT: [[V_CMP_NGT_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_NGT_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
318+
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_fake16_e64_]]
319+
%0:vgpr(s32) = COPY $vgpr0
320+
%1:vgpr(s32) = COPY $vgpr1
321+
%2:vgpr(s16) = G_TRUNC %0
322+
%3:vgpr(s16) = G_TRUNC %1
323+
%4:vcc(s1) = G_FCMP floatpred(ule), %2, %3
324+
S_ENDPGM 0, implicit %4
325+
...
326+
327+
---
328+
name: fcmp_une_s16_vv
329+
legalized: true
330+
regBankSelected: true
331+
332+
body: |
333+
bb.0:
334+
liveins: $vgpr0, $vgpr1
335+
; GFX11-LABEL: name: fcmp_une_s16_vv
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; GFX11: liveins: $vgpr0, $vgpr1
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; GFX11-NEXT: {{ $}}
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; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX11-NEXT: [[V_CMP_NEQ_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_NEQ_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
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; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_fake16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vcc(s1) = G_FCMP floatpred(une), %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: fcmp_true_s16_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX11-LABEL: name: fcmp_true_s16_vv
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; GFX11: liveins: $vgpr0, $vgpr1
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; GFX11-NEXT: {{ $}}
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; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX11-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
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; GFX11-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[TRUNC]](s16), [[TRUNC1]]
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; GFX11-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vcc(s1) = G_FCMP floatpred(true), %2, %3
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S_ENDPGM 0, implicit %4
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...
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