[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)

Author: jayfoad

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

@@ -1450,7 +1450,8 @@ bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
                                        *MF->getSubtarget().getRegisterInfo());
     return false;
-  } else if (MO.isImm()) {
+  }
+  if (MO.isImm()) {
     int64_t Val = MO.getImm();
     if (AMDGPU::isInlinableIntLiteral(Val)) {
       O << Val;

llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

@@ -568,16 +568,14 @@ class RegionMRT : public MRT {
   bool contains(MachineBasicBlock *MBB) {
     for (auto *CI : Children) {
       if (CI->isMBB()) {
-        if (MBB == CI->getMBBMRT()->getMBB()) {
+        if (MBB == CI->getMBBMRT()->getMBB())
           return true;
-        }
       } else {
-        if (CI->getRegionMRT()->contains(MBB)) {
+        if (CI->getRegionMRT()->contains(MBB))
           return true;
-        } else if (CI->getRegionMRT()->getLinearizedRegion() != nullptr &&
-                   CI->getRegionMRT()->getLinearizedRegion()->contains(MBB)) {
+        if (CI->getRegionMRT()->getLinearizedRegion() != nullptr &&
+            CI->getRegionMRT()->getLinearizedRegion()->contains(MBB))
           return true;
-        }
       }
     }
     return false;
@@ -2259,63 +2257,60 @@ MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion(
     CodeBB->addSuccessor(MergeBB);
     CurrentRegion->addMBB(CodeBB);
     return nullptr;
-  } else {
-    // Handle internal block.
-    const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
-    Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass);
-    rewriteCodeBBTerminator(CodeBB, MergeBB, CodeBBSelectReg);
-    bool IsRegionEntryBB = CurrentRegion->getEntry() == CodeBB;
-    MachineBasicBlock *IfBB = createIfBlock(MergeBB, CodeBB, CodeBB, CodeBB,
-                                            BBSelectRegIn, IsRegionEntryBB);
-    CurrentRegion->addMBB(IfBB);
-    // If this is the entry block we need to make the If block the new
-    // linearized region entry.
-    if (IsRegionEntryBB) {
-      CurrentRegion->setEntry(IfBB);
-
-      if (CurrentRegion->getHasLoop()) {
-        MachineBasicBlock *RegionExit = CurrentRegion->getExit();
-        MachineBasicBlock *ETrueBB = nullptr;
-        MachineBasicBlock *EFalseBB = nullptr;
-        SmallVector<MachineOperand, 1> ECond;
-
-        const DebugLoc &DL = DebugLoc();
-        TII->analyzeBranch(*RegionExit, ETrueBB, EFalseBB, ECond);
-        TII->removeBranch(*RegionExit);
-
-        // We need to create a backedge if there is a loop
-        Register Reg = TII->insertNE(
-            RegionExit, RegionExit->instr_end(), DL,
-            CurrentRegion->getRegionMRT()->getInnerOutputRegister(),
-            CurrentRegion->getRegionMRT()->getEntry()->getNumber());
-        MachineOperand RegOp =
-            MachineOperand::CreateReg(Reg, false, false, true);
-        ArrayRef<MachineOperand> Cond(RegOp);
-        LLVM_DEBUG(dbgs() << "RegionExitReg: ");
-        LLVM_DEBUG(RegOp.print(dbgs(), TRI));
-        LLVM_DEBUG(dbgs() << "\n");
-        TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit,
-                          Cond, DebugLoc());
-        RegionExit->addSuccessor(CurrentRegion->getEntry());
-      }
-    }
-    CurrentRegion->addMBB(CodeBB);
-    LinearizedRegion InnerRegion(CodeBB, MRI, TRI, PHIInfo);
+  }
+  // Handle internal block.
+  const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
+  Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass);
+  rewriteCodeBBTerminator(CodeBB, MergeBB, CodeBBSelectReg);
+  bool IsRegionEntryBB = CurrentRegion->getEntry() == CodeBB;
+  MachineBasicBlock *IfBB = createIfBlock(MergeBB, CodeBB, CodeBB, CodeBB,
+                                          BBSelectRegIn, IsRegionEntryBB);
+  CurrentRegion->addMBB(IfBB);
+  // If this is the entry block we need to make the If block the new
+  // linearized region entry.
+  if (IsRegionEntryBB) {
+    CurrentRegion->setEntry(IfBB);
+
+    if (CurrentRegion->getHasLoop()) {
+      MachineBasicBlock *RegionExit = CurrentRegion->getExit();
+      MachineBasicBlock *ETrueBB = nullptr;
+      MachineBasicBlock *EFalseBB = nullptr;
+      SmallVector<MachineOperand, 1> ECond;
 
-    InnerRegion.setParent(CurrentRegion);
-    LLVM_DEBUG(dbgs() << "Insert BB Select PHI (BB)\n");
-    insertMergePHI(IfBB, CodeBB, MergeBB, BBSelectRegOut, BBSelectRegIn,
-                   CodeBBSelectReg);
-    InnerRegion.addMBB(MergeBB);
+      const DebugLoc &DL = DebugLoc();
+      TII->analyzeBranch(*RegionExit, ETrueBB, EFalseBB, ECond);
+      TII->removeBranch(*RegionExit);
 
-    LLVM_DEBUG(InnerRegion.print(dbgs(), TRI));
-    rewriteLiveOutRegs(IfBB, CodeBB, MergeBB, &InnerRegion, CurrentRegion);
-    extractKilledPHIs(CodeBB);
-    if (IsRegionEntryBB) {
-      createEntryPHIs(CurrentRegion);
+      // We need to create a backedge if there is a loop
+      Register Reg =
+          TII->insertNE(RegionExit, RegionExit->instr_end(), DL,
+                        CurrentRegion->getRegionMRT()->getInnerOutputRegister(),
+                        CurrentRegion->getRegionMRT()->getEntry()->getNumber());
+      MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
+      ArrayRef<MachineOperand> Cond(RegOp);
+      LLVM_DEBUG(dbgs() << "RegionExitReg: ");
+      LLVM_DEBUG(RegOp.print(dbgs(), TRI));
+      LLVM_DEBUG(dbgs() << "\n");
+      TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit,
+                        Cond, DebugLoc());
+      RegionExit->addSuccessor(CurrentRegion->getEntry());
     }
-    return IfBB;
   }
+  CurrentRegion->addMBB(CodeBB);
+  LinearizedRegion InnerRegion(CodeBB, MRI, TRI, PHIInfo);
+
+  InnerRegion.setParent(CurrentRegion);
+  LLVM_DEBUG(dbgs() << "Insert BB Select PHI (BB)\n");
+  insertMergePHI(IfBB, CodeBB, MergeBB, BBSelectRegOut, BBSelectRegIn,
+                 CodeBBSelectReg);
+  InnerRegion.addMBB(MergeBB);
+
+  LLVM_DEBUG(InnerRegion.print(dbgs(), TRI));
+  rewriteLiveOutRegs(IfBB, CodeBB, MergeBB, &InnerRegion, CurrentRegion);
+  extractKilledPHIs(CodeBB);
+  if (IsRegionEntryBB)
+    createEntryPHIs(CurrentRegion);
+  return IfBB;
 }
 
 MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion(
@@ -2712,12 +2707,11 @@ bool AMDGPUMachineCFGStructurizer::structurizeRegion(RegionMRT *Region) {
   if (false && regionIsSimpleIf(Region)) {
     transformSimpleIfRegion(Region);
     return true;
-  } else if (regionIsSequence(Region)) {
+  }
+  if (regionIsSequence(Region))
     fixupRegionExits(Region);
-    return false;
-  } else {
+  else
     structurizeComplexRegion(Region);
-  }
   return false;
 }
 
@@ -2784,12 +2778,11 @@ AMDGPUMachineCFGStructurizer::initializeSelectRegisters(MRT *MRT, unsigned Selec
       InnerSelectOut = initializeSelectRegisters(CI, InnerSelectOut, MRI, TII);
     MRT->setBBSelectRegIn(InnerSelectOut);
     return InnerSelectOut;
-  } else {
-    MRT->setBBSelectRegOut(SelectOut);
-    unsigned NewSelectIn = createBBSelectReg(TII, MRI);
-    MRT->setBBSelectRegIn(NewSelectIn);
-    return NewSelectIn;
   }
+  MRT->setBBSelectRegOut(SelectOut);
+  unsigned NewSelectIn = createBBSelectReg(TII, MRI);
+  MRT->setBBSelectRegIn(NewSelectIn);
+  return NewSelectIn;
 }
 
 static void checkRegOnlyPHIInputs(MachineFunction &MF) {

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

@@ -1116,15 +1116,14 @@ bool AMDGPURegisterBankInfo::applyMappingLoad(
             LegalizerHelper::Legalized)
           return false;
         return true;
+      }
+      LLT WiderTy = widen96To128(LoadTy);
+      auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0);
+      if (WiderTy.isScalar()) {
+        B.buildTrunc(MI.getOperand(0), WideLoad);
       } else {
-        LLT WiderTy = widen96To128(LoadTy);
-        auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0);
-        if (WiderTy.isScalar())
-          B.buildTrunc(MI.getOperand(0), WideLoad);
-        else {
-          B.buildDeleteTrailingVectorElements(MI.getOperand(0).getReg(),
-                                              WideLoad);
-        }
+        B.buildDeleteTrailingVectorElements(MI.getOperand(0).getReg(),
+                                            WideLoad);
       }
     }
 

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

@@ -1038,15 +1038,14 @@ unsigned GCNSubtarget::getNSAThreshold(const MachineFunction &MF) const {
 const AMDGPUSubtarget &AMDGPUSubtarget::get(const MachineFunction &MF) {
   if (MF.getTarget().getTargetTriple().getArch() == Triple::amdgcn)
     return static_cast<const AMDGPUSubtarget&>(MF.getSubtarget<GCNSubtarget>());
-  else
-    return static_cast<const AMDGPUSubtarget&>(MF.getSubtarget<R600Subtarget>());
+  return static_cast<const AMDGPUSubtarget &>(MF.getSubtarget<R600Subtarget>());
 }
 
 const AMDGPUSubtarget &AMDGPUSubtarget::get(const TargetMachine &TM, const Function &F) {
   if (TM.getTargetTriple().getArch() == Triple::amdgcn)
     return static_cast<const AMDGPUSubtarget&>(TM.getSubtarget<GCNSubtarget>(F));
-  else
-    return static_cast<const AMDGPUSubtarget&>(TM.getSubtarget<R600Subtarget>(F));
+  return static_cast<const AMDGPUSubtarget &>(
+      TM.getSubtarget<R600Subtarget>(F));
 }
 
 GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(const Function &F,

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

@@ -99,13 +99,11 @@ class AMDGPUOperand : public MCParsedAsmOperand {
     int64_t getModifiersOperand() const {
       assert(!(hasFPModifiers() && hasIntModifiers())
            && "fp and int modifiers should not be used simultaneously");
-      if (hasFPModifiers()) {
+      if (hasFPModifiers())
         return getFPModifiersOperand();
-      } else if (hasIntModifiers()) {
+      if (hasIntModifiers())
         return getIntModifiersOperand();
-      } else {
-        return 0;
-      }
+      return 0;
     }
 
     friend raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods);
@@ -2162,10 +2160,9 @@ template <bool IsFake16> bool AMDGPUOperand::isT16VRegWithInputMods() const {
 bool AMDGPUOperand::isSDWAOperand(MVT type) const {
   if (AsmParser->isVI())
     return isVReg32();
-  else if (AsmParser->isGFX9Plus())
+  if (AsmParser->isGFX9Plus())
     return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type);
-  else
-    return false;
+  return false;
 }
 
 bool AMDGPUOperand::isSDWAFP16Operand() const {
@@ -3680,19 +3677,17 @@ static OperandIndices getSrcOperandIndices(unsigned Opcode,
 
 bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {
   const MCOperand &MO = Inst.getOperand(OpIdx);
-  if (MO.isImm()) {
+  if (MO.isImm())
     return !isInlineConstant(Inst, OpIdx);
-  } else if (MO.isReg()) {
+  if (MO.isReg()) {
     auto Reg = MO.getReg();
-    if (!Reg) {
+    if (!Reg)
       return false;
-    }
     const MCRegisterInfo *TRI = getContext().getRegisterInfo();
     auto PReg = mc2PseudoReg(Reg);
     return isSGPR(PReg, TRI) && PReg != SGPR_NULL;
-  } else {
-    return true;
   }
+  return true;
 }
 
 // Based on the comment for `AMDGPUInstructionSelector::selectWritelane`:
@@ -6338,16 +6333,20 @@ StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {
     setForcedDPP(true);
     setForcedEncodingSize(64);
     return Name.substr(0, Name.size() - 8);
-  } else if (Name.ends_with("_e64")) {
+  }
+  if (Name.ends_with("_e64")) {
     setForcedEncodingSize(64);
     return Name.substr(0, Name.size() - 4);
-  } else if (Name.ends_with("_e32")) {
+  }
+  if (Name.ends_with("_e32")) {
     setForcedEncodingSize(32);
     return Name.substr(0, Name.size() - 4);
-  } else if (Name.ends_with("_dpp")) {
+  }
+  if (Name.ends_with("_dpp")) {
     setForcedDPP(true);
     return Name.substr(0, Name.size() - 4);
-  } else if (Name.ends_with("_sdwa")) {
+  }
+  if (Name.ends_with("_sdwa")) {
     setForcedSDWA(true);
     return Name.substr(0, Name.size() - 5);
   }
@@ -7754,10 +7753,9 @@ AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {
     Val = getToken().getStringContents();
     lex();
     return true;
-  } else {
-    Error(getLoc(), ErrMsg);
-    return false;
   }
+  Error(getLoc(), ErrMsg);
+  return false;
 }
 
 bool
@@ -7766,11 +7764,10 @@ AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {
     Val = getTokenStr();
     lex();
     return true;
-  } else {
-    if (!ErrMsg.empty())
-      Error(getLoc(), ErrMsg);
-    return false;
   }
+  if (!ErrMsg.empty())
+    Error(getLoc(), ErrMsg);
+  return false;
 }
 
 AsmToken
@@ -9475,8 +9472,8 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
            (SkipSrcVcc && Inst.getNumOperands() == 5))) {
         SkippedVcc = true;
         continue;
-      } else if (BasicInstType == SIInstrFlags::VOPC &&
-                 Inst.getNumOperands() == 0) {
+      }
+      if (BasicInstType == SIInstrFlags::VOPC && Inst.getNumOperands() == 0) {
         SkippedVcc = true;
         continue;
       }

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

@@ -1566,8 +1566,7 @@ AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val,
     if (MandatoryLiteral)
       // Keep a sentinel value for deferred setting
       return MCOperand::createImm(LITERAL_CONST);
-    else
-      return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64);
+    return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64);
   }
 
   switch (Width) {
@@ -1701,9 +1700,9 @@ AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val,
       return decodeFPImmed(ImmWidth, SVal, Sema);
 
     return decodeSpecialReg32(SVal);
-  } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) {
-    return createRegOperand(getVgprClassId(Width), Val);
   }
+  if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands))
+    return createRegOperand(getVgprClassId(Width), Val);
   llvm_unreachable("unsupported target");
 }
 
@@ -1731,15 +1730,13 @@ MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
     if (TTmpIdx >= 0) {
       auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
       return createSRegOperand(TTmpClsId, TTmpIdx);
-    } else if (Val > SGPR_MAX) {
-      return IsWave64 ? decodeSpecialReg64(Val)
-                      : decodeSpecialReg32(Val);
-    } else {
-      return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
     }
-  } else {
-    return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
+    if (Val > SGPR_MAX) {
+      return IsWave64 ? decodeSpecialReg64(Val) : decodeSpecialReg32(Val);
+    }
+    return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
   }
+  return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
 }
 
 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
@@ -2265,7 +2262,8 @@ Expected<bool> AMDGPUDisassembler::decodeKernelDescriptorDirective(
       return createReservedKDBitsError(
           KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
           amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, "must be zero on gfx9");
-    } else if (isGFX10Plus()) {
+    }
+    if (isGFX10Plus()) {
       PRINT_DIRECTIVE(".amdhsa_wavefront_size32",
                       KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
     }