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arsenmarsenm
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AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
Many tests use store to undef as a placeholder use, so just replace all of these with poison.
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,6 @@
88
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD
99
define amdgpu_kernel void @addi32(i32 %arg1, i32 %arg2) {
1010
%res = add i32 %arg1, %arg2
11-
store i32 %res, ptr addrspace(1) undef
11+
store i32 %res, ptr addrspace(1) poison
1212
ret void
1313
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -102,11 +102,11 @@ entry:
102102
br i1 %trunc, label %bb0, label %bb1
103103

104104
bb0:
105-
store volatile i32 0, ptr addrspace(1) undef
105+
store volatile i32 0, ptr addrspace(1) poison
106106
unreachable
107107

108108
bb1:
109-
store volatile i32 1, ptr addrspace(1) undef
109+
store volatile i32 1, ptr addrspace(1) poison
110110
unreachable
111111
}
112112

@@ -153,10 +153,10 @@ entry:
153153
br i1 %and, label %bb0, label %bb1
154154

155155
bb0:
156-
store volatile i32 0, ptr addrspace(1) undef
156+
store volatile i32 0, ptr addrspace(1) poison
157157
unreachable
158158

159159
bb1:
160-
store volatile i32 1, ptr addrspace(1) undef
160+
store volatile i32 1, ptr addrspace(1) poison
161161
unreachable
162162
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ define float @v_uitofp_to_f32_multi_use_lshr8_mask255(i32 %arg0) nounwind {
9696
; VI-NEXT: s_waitcnt vmcnt(0)
9797
; VI-NEXT: s_setpc_b64 s[30:31]
9898
%lshr.8 = lshr i32 %arg0, 8
99-
store i32 %lshr.8, ptr addrspace(1) undef
99+
store i32 %lshr.8, ptr addrspace(1) poison
100100
%masked = and i32 %lshr.8, 255
101101
%cvt = uitofp i32 %masked to float
102102
ret float %cvt

‎llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ entry:
2222
br i1 %c, label %if.true, label %endif
2323

2424
if.true:
25-
%val = load volatile i32, ptr addrspace(1) undef
25+
%val = load volatile i32, ptr addrspace(1) poison
2626
br label %endif
2727

2828
endif:
@@ -53,7 +53,7 @@ endif:
5353
ret i32 %v
5454

5555
if.true:
56-
%val = load volatile i32, ptr addrspace(1) undef
56+
%val = load volatile i32, ptr addrspace(1) poison
5757
br label %endif
5858
}
5959

@@ -78,7 +78,7 @@ entry:
7878
br i1 %c, label %if.true, label %endif
7979

8080
if.true:
81-
%val = load volatile i32, ptr addrspace(1) undef
81+
%val = load volatile i32, ptr addrspace(1) poison
8282
br label %endif
8383

8484
endif:
@@ -110,7 +110,7 @@ entry:
110110
br i1 %c, label %if.true, label %endif
111111

112112
if.true:
113-
%val = load volatile i32, ptr addrspace(1) undef
113+
%val = load volatile i32, ptr addrspace(1) poison
114114
br label %endif
115115

116116
endif:
@@ -237,7 +237,7 @@ bb1:
237237
br i1 %cmp0, label %bb4, label %bb9
238238

239239
bb4:
240-
%load = load volatile i32, ptr addrspace(1) undef, align 4
240+
%load = load volatile i32, ptr addrspace(1) poison, align 4
241241
%cmp1 = icmp slt i32 %tmp, %load
242242
br i1 %cmp1, label %bb1, label %bb9
243243

‎llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -483,7 +483,7 @@ define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) {
483483
; GFX11-NEXT: s_endpgm
484484
entry:
485485
%ext = extractelement <8 x i64> <i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8>, i32 %sel
486-
store i64 %ext, ptr addrspace(1) undef
486+
store i64 %ext, ptr addrspace(1) poison
487487
ret void
488488
}
489489

@@ -628,7 +628,7 @@ define amdgpu_ps void @dyn_extract_v8i64_s_v(<8 x i64> inreg %vec, i32 %sel) {
628628
; GFX11-NEXT: s_endpgm
629629
entry:
630630
%ext = extractelement <8 x i64> %vec, i32 %sel
631-
store i64 %ext, ptr addrspace(1) undef
631+
store i64 %ext, ptr addrspace(1) poison
632632
ret void
633633
}
634634

@@ -744,7 +744,7 @@ define amdgpu_ps void @dyn_extract_v8i64_v_s(<8 x i64> %vec, i32 inreg %sel) {
744744
; GFX11-NEXT: s_endpgm
745745
entry:
746746
%ext = extractelement <8 x i64> %vec, i32 %sel
747-
store i64 %ext, ptr addrspace(1) undef
747+
store i64 %ext, ptr addrspace(1) poison
748748
ret void
749749
}
750750

@@ -849,7 +849,7 @@ define amdgpu_ps void @dyn_extract_v8i64_s_s(<8 x i64> inreg %vec, i32 inreg %se
849849
; GFX11-NEXT: s_endpgm
850850
entry:
851851
%ext = extractelement <8 x i64> %vec, i32 %sel
852-
store i64 %ext, ptr addrspace(1) undef
852+
store i64 %ext, ptr addrspace(1) poison
853853
ret void
854854
}
855855

@@ -1800,7 +1800,7 @@ define amdgpu_ps void @dyn_extract_v8p1_s_s(<8 x ptr addrspace(1)> inreg %vec, i
18001800
; GFX11-NEXT: s_endpgm
18011801
entry:
18021802
%ext = extractelement <8 x ptr addrspace(1)> %vec, i32 %idx
1803-
store ptr addrspace(1) %ext, ptr addrspace(1) undef
1803+
store ptr addrspace(1) %ext, ptr addrspace(1) poison
18041804
ret void
18051805
}
18061806

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