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Thorsten Schütt
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address review comments
1 parent a03e473 commit 68a0152

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-25
lines changed

3 files changed

+246
-25
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‎llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -546,8 +546,10 @@ class IRTranslator : public MachineFunctionPass {
546546
bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder);
547547

548548
bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder);
549+
bool translateInsertVector(const User &U, MachineIRBuilder &MIRBuilder);
549550

550551
bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
552+
bool translateExtractVector(const User &U, MachineIRBuilder &MIRBuilder);
551553

552554
bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
553555

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 107 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2588,20 +2588,10 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
25882588
getOrCreateVReg(*CI.getOperand(0)),
25892589
getOrCreateVReg(*CI.getOperand(1)));
25902590
return true;
2591-
case Intrinsic::vector_extract: {
2592-
ConstantInt *Index = cast<ConstantInt>(CI.getOperand(1));
2593-
MIRBuilder.buildExtractSubvector(getOrCreateVReg(CI),
2594-
getOrCreateVReg(*CI.getOperand(0)),
2595-
Index->getZExtValue());
2596-
return true;
2597-
}
2598-
case Intrinsic::vector_insert: {
2599-
ConstantInt *Index = cast<ConstantInt>(CI.getOperand(2));
2600-
MIRBuilder.buildInsertSubvector(
2601-
getOrCreateVReg(CI), getOrCreateVReg(*CI.getOperand(0)),
2602-
getOrCreateVReg(*CI.getOperand(1)), Index->getZExtValue());
2603-
return true;
2604-
}
2591+
case Intrinsic::vector_extract:
2592+
return translateExtractVector(CI, MIRBuilder);
2593+
case Intrinsic::vector_insert:
2594+
return translateInsertVector(CI, MIRBuilder);
26052595
case Intrinsic::prefetch: {
26062596
Value *Addr = CI.getOperand(0);
26072597
unsigned RW = cast<ConstantInt>(CI.getOperand(1))->getZExtValue();
@@ -3163,8 +3153,7 @@ bool IRTranslator::translateInsertElement(const User &U,
31633153
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(2))) {
31643154
if (CI->getBitWidth() != PreferredVecIdxWidth) {
31653155
APInt NewIdx = CI->getValue().zextOrTrunc(PreferredVecIdxWidth);
3166-
auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx);
3167-
Idx = getOrCreateVReg(*NewIdxCI);
3156+
CI = ConstantInt::get(CI->getContext(), NewIdx);
31683157
}
31693158
}
31703159
if (!Idx)
@@ -3177,6 +3166,58 @@ bool IRTranslator::translateInsertElement(const User &U,
31773166
return true;
31783167
}
31793168

3169+
bool IRTranslator::translateInsertVector(const User &U,
3170+
MachineIRBuilder &MIRBuilder) {
3171+
Register Dst = getOrCreateVReg(U);
3172+
Register Vec = getOrCreateVReg(*U.getOperand(0));
3173+
Register Elt = getOrCreateVReg(*U.getOperand(1));
3174+
3175+
ConstantInt *CI = cast<ConstantInt>(U.getOperand(2));
3176+
unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
3177+
3178+
// Resize Index to preferred index width.
3179+
if (CI->getBitWidth() != PreferredVecIdxWidth) {
3180+
APInt NewIdx = CI->getValue().zextOrTrunc(PreferredVecIdxWidth);
3181+
CI = ConstantInt::get(CI->getContext(), NewIdx);
3182+
}
3183+
3184+
// If it is a <1 x Ty> vector, we have to use other means.
3185+
if (auto *ResultType = dyn_cast<FixedVectorType>(U.getOperand(1)->getType());
3186+
ResultType && ResultType->getNumElements() == 1) {
3187+
if (auto *InputType = dyn_cast<FixedVectorType>(U.getOperand(0)->getType());
3188+
InputType && InputType->getNumElements() == 1) {
3189+
// We are inserting an illegal fixed vector into an illegal
3190+
// fixed vector, use the scalar as it is not a legal vector type
3191+
// in LLT.
3192+
return translateCopy(U, *U.getOperand(0), MIRBuilder);
3193+
}
3194+
if (auto *InputType =
3195+
dyn_cast<FixedVectorType>(U.getOperand(0)->getType())) {
3196+
// We are inserting an illegal fixed vector into a fixed vector, use the
3197+
// scalar as it is not a legal vector type in LLT.
3198+
Register Idx = getOrCreateVReg(*CI);
3199+
MIRBuilder.buildInsertVectorElement(Dst, Vec, Elt, Idx);
3200+
return true;
3201+
}
3202+
if (auto *InputType =
3203+
dyn_cast<ScalableVectorType>(U.getOperand(0)->getType())) {
3204+
// We are inserting an illegal fixed vector into a scalable vector, use
3205+
// a scalar element insert.
3206+
LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
3207+
Register Idx = getOrCreateVReg(*CI);
3208+
auto ScaledIndex = MIRBuilder.buildMul(
3209+
VecIdxTy, MIRBuilder.buildVScale(VecIdxTy, 1), Idx);
3210+
MIRBuilder.buildInsertVectorElement(Dst, Vec, Elt, ScaledIndex);
3211+
return true;
3212+
}
3213+
}
3214+
3215+
MIRBuilder.buildInsertSubvector(
3216+
getOrCreateVReg(U), getOrCreateVReg(*U.getOperand(0)),
3217+
getOrCreateVReg(*U.getOperand(1)), CI->getZExtValue());
3218+
return true;
3219+
}
3220+
31803221
bool IRTranslator::translateExtractElement(const User &U,
31813222
MachineIRBuilder &MIRBuilder) {
31823223
// If it is a <1 x Ty> vector, use the scalar as it is
@@ -3205,6 +3246,56 @@ bool IRTranslator::translateExtractElement(const User &U,
32053246
return true;
32063247
}
32073248

3249+
bool IRTranslator::translateExtractVector(const User &U,
3250+
MachineIRBuilder &MIRBuilder) {
3251+
Register Res = getOrCreateVReg(U);
3252+
Register Vec = getOrCreateVReg(*U.getOperand(0));
3253+
ConstantInt *CI = cast<ConstantInt>(U.getOperand(1));
3254+
unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
3255+
3256+
// Resize Index to preferred index width.
3257+
if (CI->getBitWidth() != PreferredVecIdxWidth) {
3258+
APInt NewIdx = CI->getValue().zextOrTrunc(PreferredVecIdxWidth);
3259+
CI = ConstantInt::get(CI->getContext(), NewIdx);
3260+
}
3261+
3262+
// If it is a <1 x Ty> vector, we have to use other means.
3263+
if (auto *ResultType = dyn_cast<FixedVectorType>(U.getType());
3264+
ResultType && ResultType->getNumElements() == 1) {
3265+
if (auto *InputType = dyn_cast<FixedVectorType>(U.getOperand(0)->getType());
3266+
InputType && InputType->getNumElements() == 1) {
3267+
// We are extracting an illegal fixed vector from an illegal fixed vector,
3268+
// use the scalar as it is not a legal vector type in LLT.
3269+
return translateCopy(U, *U.getOperand(0), MIRBuilder);
3270+
}
3271+
if (auto *InputType =
3272+
dyn_cast<FixedVectorType>(U.getOperand(0)->getType())) {
3273+
// We are extracting a fixed vector from a fixed vector, use the
3274+
// scalar as it is not a legal vector type in LLT.
3275+
Register Idx = getOrCreateVReg(*CI);
3276+
MIRBuilder.buildExtractVectorElement(Res, Vec, Idx);
3277+
return true;
3278+
}
3279+
if (auto *InputType =
3280+
dyn_cast<ScalableVectorType>(U.getOperand(0)->getType())) {
3281+
// We are extracting a fixed vector from a scalable vector, use
3282+
// a scalar element extract.
3283+
LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
3284+
Register Idx = getOrCreateVReg(*CI);
3285+
auto ScaledIndex = MIRBuilder.buildMul(
3286+
VecIdxTy, MIRBuilder.buildVScale(VecIdxTy, 1), Idx);
3287+
MIRBuilder.buildExtractVectorElement(Res, Vec, ScaledIndex);
3288+
return true;
3289+
}
3290+
}
3291+
3292+
ConstantInt *Index = cast<ConstantInt>(U.getOperand(1));
3293+
MIRBuilder.buildExtractSubvector(getOrCreateVReg(U),
3294+
getOrCreateVReg(*U.getOperand(0)),
3295+
Index->getZExtValue());
3296+
return true;
3297+
}
3298+
32083299
bool IRTranslator::translateShuffleVector(const User &U,
32093300
MachineIRBuilder &MIRBuilder) {
32103301
// A ShuffleVector that operates on scalable vectors is a splat vector where

‎llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll

Lines changed: 137 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
2+
; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve -global-isel -stop-after=irtranslator -aarch64-enable-gisel-sve=1 %s -o - | FileCheck %s
33

44
define i32 @extract_v4i32_vector_insert_const(<4 x i32> %a, <2 x i32> %b, i32 %c) {
55
; CHECK-LABEL: name: extract_v4i32_vector_insert_const
@@ -58,21 +58,149 @@ entry:
5858
ret i32 %d
5959
}
6060

61-
define i32 @extract_v4i32_vector_extract_const(<4 x i32> %a, <2 x i32> %b, i32 %c) {
61+
define i32 @extract_v4i32_vector_extract_const(<vscale x 4 x i32> %a, i32 %c, ptr %p) {
6262
; CHECK-LABEL: name: extract_v4i32_vector_extract_const
6363
; CHECK: bb.1.entry:
64-
; CHECK-NEXT: liveins: $d1, $q0, $w0
64+
; CHECK-NEXT: liveins: $w0, $x1, $z0
65+
; CHECK-NEXT: {{ $}}
66+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
67+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
68+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
69+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
70+
; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 4 x s32>), 0
71+
; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 4 x s32>), [[COPY2]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)
72+
; CHECK-NEXT: $w0 = COPY [[C]](s32)
73+
; CHECK-NEXT: RET_ReallyLR implicit $w0
74+
entry:
75+
%vector = call <vscale x 4 x i32> @llvm.vector.extract(<vscale x 4 x i32> %a, i64 0)
76+
store <vscale x 4 x i32> %vector, ptr %p, align 16
77+
ret i32 1
78+
}
79+
80+
define i32 @extract_v4i32_vector_insert_const_vscale(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 %c, ptr %p) {
81+
; CHECK-LABEL: name: extract_v4i32_vector_insert_const_vscale
82+
; CHECK: bb.1.entry:
83+
; CHECK-NEXT: liveins: $w0, $x1, $z0, $z1
84+
; CHECK-NEXT: {{ $}}
85+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
86+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
87+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
88+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
89+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
90+
; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<vscale x 4 x s32>), 0
91+
; CHECK-NEXT: G_STORE [[INSERT_SUBVECTOR]](<vscale x 4 x s32>), [[COPY3]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)
92+
; CHECK-NEXT: $w0 = COPY [[C]](s32)
93+
; CHECK-NEXT: RET_ReallyLR implicit $w0
94+
entry:
95+
%vector = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i64 0)
96+
store <vscale x 4 x i32> %vector, ptr %p, align 16
97+
ret i32 1
98+
}
99+
100+
define i32 @extract_v4i32_vector_extract_const_illegal_fixed(<4 x i32> %a, ptr %p) {
101+
; CHECK-LABEL: name: extract_v4i32_vector_extract_const_illegal_fixed
102+
; CHECK: bb.1.entry:
103+
; CHECK-NEXT: liveins: $q0, $x0
104+
; CHECK-NEXT: {{ $}}
105+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
106+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
107+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
108+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
109+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64)
110+
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[COPY1]](p0) :: (store (s32) into %ir.p, align 16)
111+
; CHECK-NEXT: $w0 = COPY [[C1]](s32)
112+
; CHECK-NEXT: RET_ReallyLR implicit $w0
113+
entry:
114+
%vector = call <1 x i32> @llvm.vector.extract(<4 x i32> %a, i64 0)
115+
store <1 x i32> %vector, ptr %p, align 16
116+
ret i32 1
117+
}
118+
119+
define i32 @extract_v4i32_vector_extract_const_illegal_scalable(<vscale x 4 x i32> %a, ptr %p) {
120+
; CHECK-LABEL: name: extract_v4i32_vector_extract_const_illegal_scalable
121+
; CHECK: bb.1.entry:
122+
; CHECK-NEXT: liveins: $x0, $z0
123+
; CHECK-NEXT: {{ $}}
124+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
125+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
126+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
127+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
128+
; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
129+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]
130+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s32>), [[MUL]](s64)
131+
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[COPY1]](p0) :: (store (s32) into %ir.p, align 16)
132+
; CHECK-NEXT: $w0 = COPY [[C1]](s32)
133+
; CHECK-NEXT: RET_ReallyLR implicit $w0
134+
entry:
135+
%vector = call <1 x i32> @llvm.vector.extract(<vscale x 4 x i32> %a, i64 0)
136+
store <1 x i32> %vector, ptr %p, align 16
137+
ret i32 1
138+
}
139+
140+
define i32 @extract_v4i32_vector_insert_const_illegal_scalable(<vscale x 4 x i32> %a, <1 x i32> %b, i32 %c, ptr %p) {
141+
; CHECK-LABEL: name: extract_v4i32_vector_insert_const_illegal_scalable
142+
; CHECK: bb.1.entry:
143+
; CHECK-NEXT: liveins: $d1, $w0, $x1, $z0
144+
; CHECK-NEXT: {{ $}}
145+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
146+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
147+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
148+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
149+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
150+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
151+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
152+
; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
153+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]
154+
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](s32), [[MUL]](s64)
155+
; CHECK-NEXT: G_STORE [[IVEC]](<vscale x 4 x s32>), [[COPY3]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)
156+
; CHECK-NEXT: $w0 = COPY [[C1]](s32)
157+
; CHECK-NEXT: RET_ReallyLR implicit $w0
158+
entry:
159+
%vector = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %a, <1 x i32> %b, i64 0)
160+
store <vscale x 4 x i32> %vector, ptr %p, align 16
161+
ret i32 1
162+
}
163+
164+
define i32 @extract_v4i32_vector_insert_const_fixed(<4 x i32> %a, <1 x i32> %b, i32 %c, ptr %p) {
165+
; CHECK-LABEL: name: extract_v4i32_vector_insert_const_fixed
166+
; CHECK: bb.1.entry:
167+
; CHECK-NEXT: liveins: $d1, $q0, $w0, $x1
65168
; CHECK-NEXT: {{ $}}
66169
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
67170
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
171+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
68172
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
173+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
69174
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
70-
; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<4 x s32>), 0
71-
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[EXTRACT_SUBVECTOR]](<4 x s32>), [[C]](s64)
72-
; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
175+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
176+
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](s32), [[C]](s64)
177+
; CHECK-NEXT: G_STORE [[IVEC]](<4 x s32>), [[COPY3]](p0) :: (store (<4 x s32>) into %ir.p)
178+
; CHECK-NEXT: $w0 = COPY [[C1]](s32)
73179
; CHECK-NEXT: RET_ReallyLR implicit $w0
74180
entry:
75-
%vector = call <4 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %a, i64 0)
76-
%d = extractelement <4 x i32> %vector, i32 0
77-
ret i32 %d
181+
%vector = call <4 x i32> @llvm.vector.insert.v4i32.v4i32(<4 x i32> %a, <1 x i32> %b, i64 0)
182+
store <4 x i32> %vector, ptr %p, align 16
183+
ret i32 1
184+
}
185+
186+
define i32 @extract_v4i32_vector_insert_const_fixed_illegal(<1 x i32> %a, <1 x i32> %b, i32 %c, ptr %p) {
187+
; CHECK-LABEL: name: extract_v4i32_vector_insert_const_fixed_illegal
188+
; CHECK: bb.1.entry:
189+
; CHECK-NEXT: liveins: $d0, $d1, $w0, $x1
190+
; CHECK-NEXT: {{ $}}
191+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
192+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
193+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
194+
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
195+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
196+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
197+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
198+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
199+
; CHECK-NEXT: G_STORE [[COPY4]](s32), [[COPY3]](p0) :: (store (s32) into %ir.p, align 16)
200+
; CHECK-NEXT: $w0 = COPY [[C]](s32)
201+
; CHECK-NEXT: RET_ReallyLR implicit $w0
202+
entry:
203+
%vector = call <1 x i32> @llvm.vector.insert.v1i32.v4i32(<1 x i32> %a, <1 x i32> %b, i64 0)
204+
store <1 x i32> %vector, ptr %p, align 16
205+
ret i32 1
78206
}

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