[Xtensa] Implement lowering llvm intrinsics fshr/fshl.

Author: andreisfr

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

@@ -188,6 +188,10 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
   setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
   setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
 
+  // Funnel shifts
+  setOperationAction(ISD::FSHR, MVT::i32, Custom);
+  setOperationAction(ISD::FSHL, MVT::i32, Custom);
+
   // Bit Manipulation
   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
   setOperationAction(ISD::BSWAP, MVT::i64, Expand);
@@ -1674,6 +1678,23 @@ SDValue XtensaTargetLowering::LowerShiftRightParts(SDValue Op,
   return DAG.getMergeValues(Ops, DL);
 }
 
+SDValue XtensaTargetLowering::LowerFunnelShift(SDValue Op,
+                                               SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  SDValue Op0 = Op.getOperand(0);
+  SDValue Op1 = Op.getOperand(1);
+  SDValue Shamt = Op.getOperand(2);
+  MVT VT = Op.getSimpleValueType();
+
+  bool IsFSHR = Op.getOpcode() == ISD::FSHR;
+  assert((VT == MVT::i32) && "Unexpected funnel shift type!");
+
+  SDValue SetSAR = DAG.getNode(IsFSHR ? XtensaISD::SSR : XtensaISD::SSL, DL,
+                               MVT::Glue, Shamt);
+  return DAG.getNode(XtensaISD::SRC, DL, VT, IsFSHR ? Op0 : Op1,
+                     IsFSHR ? Op1 : Op0, SetSAR);
+} 
+
 SDValue XtensaTargetLowering::LowerATOMIC_FENCE(SDValue Op,
                                                 SelectionDAG &DAG) const {
   SDLoc DL(Op);
@@ -1728,6 +1749,9 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
     return LowerShiftRightParts(Op, DAG, true);
   case ISD::SRL_PARTS:
     return LowerShiftRightParts(Op, DAG, false);
+  case ISD::FSHL:
+  case ISD::FSHR:
+    return LowerFunnelShift(Op, DAG);
   default:
     llvm_unreachable("Unexpected node to lower");
   }

llvm/lib/Target/Xtensa/XtensaISelLowering.h

@@ -195,6 +195,7 @@ class XtensaTargetLowering : public TargetLowering {
 
   SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
+  SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
 

llvm/test/CodeGen/Xtensa/funnel-shift.ll

@@ -0,0 +1,22 @@
+; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s
+
+define dso_local i32 @test_fshr(i32 %value, i32 %shift) nounwind {
+; CHECK-LABEL: @test_fshr
+; CHECK: ssr a3
+; CHECK: src a2, a2, a2
+entry:
+  %0 = tail call i32 @llvm.fshr.i32(i32 %value, i32 %value, i32 %shift)
+  ret i32 %0
+}
+
+define dso_local i32 @test_fshl(i32 %value, i32 %shift) nounwind {
+; CHECK-LABEL: @test_fshl
+; CHECK: ssl a3
+; CHECK: src a2, a2, a2
+entry:
+  %0 = tail call i32 @llvm.fshl.i32(i32 %value, i32 %value, i32 %shift)
+  ret i32 %0
+}
+
+declare i32 @llvm.fshr.i32(i32, i32, i32) nounwind
+declare i32 @llvm.fshl.i32(i32, i32, i32) nounwind