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arsenmarsenm
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Mips: Switch to RegClassByHwMode
1 parent 80bbfae commit 6fbe887

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7 files changed

+76
-36
lines changed

7 files changed

+76
-36
lines changed

‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3706,7 +3706,9 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
37063706
MCRegister TmpReg = DstReg;
37073707

37083708
const MCInstrDesc &Desc = MII.get(OpCode);
3709-
int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
3709+
int16_t DstRegClass =
3710+
MII.getOpRegClassID(Desc.operands()[StartOp],
3711+
STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
37103712
unsigned DstRegClassID =
37113713
getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
37123714
bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
@@ -3834,7 +3836,10 @@ void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
38343836
MCRegister TmpReg = DstReg;
38353837

38363838
const MCInstrDesc &Desc = MII.get(OpCode);
3837-
int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
3839+
int16_t DstRegClass =
3840+
MII.getOpRegClassID(Desc.operands()[StartOp],
3841+
STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
3842+
38383843
unsigned DstRegClassID =
38393844
getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
38403845
bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||

‎llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -916,6 +916,30 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
916916
return MCDisassembler::Success;
917917
}
918918

919+
static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
920+
uint64_t Address,
921+
const MCDisassembler *Decoder) {
922+
llvm_unreachable("this is unused");
923+
}
924+
925+
static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
926+
uint64_t Address,
927+
const MCDisassembler *Decoder) {
928+
llvm_unreachable("this is unused");
929+
}
930+
931+
static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
932+
uint64_t Address,
933+
const MCDisassembler *Decoder) {
934+
llvm_unreachable("this is unused");
935+
}
936+
937+
static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
938+
uint64_t Address,
939+
const MCDisassembler *Decoder) {
940+
llvm_unreachable("this is unused");
941+
}
942+
919943
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
920944
uint64_t Address,
921945
const MCDisassembler *Decoder) {

‎llvm/lib/Target/Mips/MicroMipsInstrInfo.td‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -57,12 +57,6 @@ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
5757
let PredicateMethod = "isMemWithGRPMM16Base";
5858
}
5959

60-
// Define the classes of pointers used by microMIPS.
61-
// The numbers must match those in MipsRegisterInfo::MipsPtrClass.
62-
def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
63-
def ptr_sp_rc : PointerLikeRegClass<2>;
64-
def ptr_gp_rc : PointerLikeRegClass<3>;
65-
6660
class mem_mm_4_generic : Operand<i32> {
6761
let PrintMethod = "printMemOperand";
6862
let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
@@ -114,7 +108,7 @@ def mem_mm_gp_simm7_lsl2 : Operand<i32> {
114108

115109
def mem_mm_9 : Operand<i32> {
116110
let PrintMethod = "printMemOperand";
117-
let MIOperandInfo = (ops ptr_rc, simm9);
111+
let MIOperandInfo = (ops mips_ptr_rc, simm9);
118112
let EncoderMethod = "getMemEncodingMMImm9";
119113
let ParserMatchClass = MipsMemSimmAsmOperand<9>;
120114
let OperandType = "OPERAND_MEMORY";
@@ -130,15 +124,15 @@ def mem_mm_11 : Operand<i32> {
130124

131125
def mem_mm_12 : Operand<i32> {
132126
let PrintMethod = "printMemOperand";
133-
let MIOperandInfo = (ops ptr_rc, simm12);
127+
let MIOperandInfo = (ops mips_ptr_rc, simm12);
134128
let EncoderMethod = "getMemEncodingMMImm12";
135129
let ParserMatchClass = MipsMemAsmOperand;
136130
let OperandType = "OPERAND_MEMORY";
137131
}
138132

139133
def mem_mm_16 : Operand<i32> {
140134
let PrintMethod = "printMemOperand";
141-
let MIOperandInfo = (ops ptr_rc, simm16);
135+
let MIOperandInfo = (ops mips_ptr_rc, simm16);
142136
let EncoderMethod = "getMemEncodingMMImm16";
143137
let DecoderMethod = "DecodeMemMMImm16";
144138
let ParserMatchClass = MipsMemSimmAsmOperand<16>;

‎llvm/lib/Target/Mips/Mips.td‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,21 @@ def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",
211211
def FeatureStrictAlign
212212
: SubtargetFeature<"strict-align", "StrictAlign", "true",
213213
"Disable unaligned load store for r6">;
214+
//===----------------------------------------------------------------------===//
215+
// Mips Instruction Predicate Definitions.
216+
//===----------------------------------------------------------------------===//
217+
218+
def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">,
219+
AssemblerPredicate<(all_of FeaturePTR64Bit)>;
220+
def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">,
221+
AssemblerPredicate<(all_of (not FeaturePTR64Bit))>;
222+
223+
//===----------------------------------------------------------------------===//
224+
// HwModes
225+
//===----------------------------------------------------------------------===//
226+
227+
defvar MIPS32 = DefaultMode;
228+
def MIPS64 : HwMode<[IsPTR64bit]>;
214229

215230
//===----------------------------------------------------------------------===//
216231
// Register File, Calling Conv, Instruction Descriptions

‎llvm/lib/Target/Mips/MipsInstrInfo.td‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,8 @@ def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
156156
//===----------------------------------------------------------------------===//
157157
// Mips Instruction Predicate Definitions.
158158
//===----------------------------------------------------------------------===//
159+
// FIXME: Move to Mips.td
160+
159161
def HasMips2 : Predicate<"Subtarget->hasMips2()">,
160162
AssemblerPredicate<(all_of FeatureMips2)>;
161163
def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
@@ -188,10 +190,6 @@ def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
188190
AssemblerPredicate<(all_of FeatureGP64Bit)>;
189191
def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
190192
AssemblerPredicate<(all_of (not FeatureGP64Bit))>;
191-
def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">,
192-
AssemblerPredicate<(all_of FeaturePTR64Bit)>;
193-
def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">,
194-
AssemblerPredicate<(all_of (not FeaturePTR64Bit))>;
195193
def HasMips64 : Predicate<"Subtarget->hasMips64()">,
196194
AssemblerPredicate<(all_of FeatureMips64)>;
197195
def NotMips64 : Predicate<"!Subtarget->hasMips64()">,
@@ -1125,7 +1123,7 @@ def InvertedImOperand64 : Operand<i64> {
11251123

11261124
class mem_generic : Operand<iPTR> {
11271125
let PrintMethod = "printMemOperand";
1128-
let MIOperandInfo = (ops ptr_rc, simm16);
1126+
let MIOperandInfo = (ops mips_ptr_rc, simm16);
11291127
let EncoderMethod = "getMemEncoding";
11301128
let ParserMatchClass = MipsMemAsmOperand;
11311129
let OperandType = "OPERAND_MEMORY";
@@ -1136,7 +1134,7 @@ def mem : mem_generic;
11361134

11371135
// MSA specific address operand
11381136
def mem_msa : mem_generic {
1139-
let MIOperandInfo = (ops ptr_rc, simm10);
1137+
let MIOperandInfo = (ops mips_ptr_rc, simm10);
11401138
let EncoderMethod = "getMSAMemEncoding";
11411139
}
11421140

@@ -1145,21 +1143,21 @@ def simm12 : Operand<i32> {
11451143
}
11461144

11471145
def mem_simm9_exp : mem_generic {
1148-
let MIOperandInfo = (ops ptr_rc, simm9);
1146+
let MIOperandInfo = (ops mips_ptr_rc, simm9);
11491147
let ParserMatchClass = MipsMemSimmPtrAsmOperand;
11501148
let OperandNamespace = "MipsII";
11511149
let OperandType = "OPERAND_MEM_SIMM9";
11521150
}
11531151

11541152
foreach I = {9, 10, 11, 12, 16} in
11551153
def mem_simm # I : mem_generic {
1156-
let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm" # I));
1154+
let MIOperandInfo = (ops mips_ptr_rc, !cast<Operand>("simm" # I));
11571155
let ParserMatchClass = MipsMemSimmAsmOperand<I>;
11581156
}
11591157

11601158
foreach I = {1, 2, 3} in
11611159
def mem_simm10_lsl # I : mem_generic {
1162-
let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm10_lsl" # I));
1160+
let MIOperandInfo = (ops mips_ptr_rc, !cast<Operand>("simm10_lsl" # I));
11631161
let EncoderMethod = "getMemEncoding<" # I # ">";
11641162
let ParserMatchClass = MipsMemSimmAsmOperand<10, I>;
11651163
}
@@ -1170,13 +1168,13 @@ def mem_simmptr : mem_generic {
11701168

11711169
def mem_ea : Operand<iPTR> {
11721170
let PrintMethod = "printMemOperandEA";
1173-
let MIOperandInfo = (ops ptr_rc, simm16);
1171+
let MIOperandInfo = (ops mips_ptr_rc, simm16);
11741172
let EncoderMethod = "getMemEncoding";
11751173
let OperandType = "OPERAND_MEMORY";
11761174
}
11771175

11781176
def PtrRC : Operand<iPTR> {
1179-
let MIOperandInfo = (ops ptr_rc);
1177+
let MIOperandInfo = (ops mips_ptr_rc);
11801178
let DecoderMethod = "DecodePtrRegisterClass";
11811179
let ParserMatchClass = GPR32AsmOperand;
11821180
}

‎llvm/lib/Target/Mips/MipsRegisterInfo.cpp‎

Lines changed: 2 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -46,20 +46,8 @@ unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
4646

4747
const TargetRegisterClass *
4848
MipsRegisterInfo::getPointerRegClass(unsigned Kind) const {
49-
MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
50-
51-
switch (PtrClassKind) {
52-
case MipsPtrClass::Default:
53-
return ArePtrs64bit ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
54-
case MipsPtrClass::GPR16MM:
55-
return &Mips::GPRMM16RegClass;
56-
case MipsPtrClass::StackPointer:
57-
return ArePtrs64bit ? &Mips::SP64RegClass : &Mips::SP32RegClass;
58-
case MipsPtrClass::GlobalPointer:
59-
return ArePtrs64bit ? &Mips::GP64RegClass : &Mips::GP32RegClass;
60-
}
61-
62-
llvm_unreachable("Unknown pointer kind");
49+
assert(Kind == 0 && "this should only be used for default case");
50+
return ArePtrs64bit ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
6351
}
6452

6553
unsigned

‎llvm/lib/Target/Mips/MipsRegisterInfo.td‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -758,3 +758,19 @@ def MSA128DOpnd : RegisterOperand<MSA128D> {
758758
def MSA128CROpnd : RegisterOperand<MSACtrl> {
759759
let ParserMatchClass = MSACtrlAsmOperand;
760760
}
761+
762+
def mips_ptr_rc : RegClassByHwMode<
763+
[MIPS32, MIPS64],
764+
[GPR32, GPR64]>;
765+
766+
def ptr_gpr16mm_rc : RegClassByHwMode<
767+
[MIPS32, MIPS64],
768+
[GPRMM16, GPRMM16]>; // FIXME: Why even use this if it's just a constant
769+
770+
def ptr_sp_rc : RegClassByHwMode<
771+
[MIPS32, MIPS64],
772+
[SP32, SP64]>;
773+
774+
def ptr_gp_rc : RegClassByHwMode<
775+
[MIPS32, MIPS64],
776+
[GP32, GP64]>;

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