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metkarpoonamV-FEXrt
metkarpoonam
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V-FEXrt
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Hlsl asint16 intrinsic (#131900)
Implemented the asint16 function and added test cases for codegen, Sema, and SPIR-V backend. fixes #99184 --------- Co-authored-by: Ashley Coleman <[email protected]>
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‎clang/lib/Headers/hlsl/hlsl_intrinsics.h

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@@ -46,6 +46,35 @@ template <typename T> constexpr int asint(T F) {
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return __detail::bit_cast<int, T>(F);
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}
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//===----------------------------------------------------------------------===//
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// asint16 builtins
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//===----------------------------------------------------------------------===//
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/// \fn int16_t asint16(T X)
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/// \brief Interprets the bit pattern of \a X as an 16-bit integer.
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/// \param X The input value.
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#ifdef __HLSL_ENABLE_16_BIT
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template <typename T, int N>
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_HLSL_16BIT_AVAILABILITY(shadermodel, 6.2)
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constexpr __detail::enable_if_t<__detail::is_same<int16_t, T>::value ||
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__detail::is_same<uint16_t, T>::value ||
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__detail::is_same<half, T>::value,
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vector<int16_t, N>> asint16(vector<T, N> V) {
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return __detail::bit_cast<int16_t, T, N>(V);
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}
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template <typename T>
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_HLSL_16BIT_AVAILABILITY(shadermodel, 6.2)
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constexpr __detail::enable_if_t<__detail::is_same<int16_t, T>::value ||
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__detail::is_same<uint16_t, T>::value ||
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__detail::is_same<half, T>::value,
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int16_t> asint16(T F) {
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return __detail::bit_cast<int16_t, T>(F);
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}
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#endif
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//===----------------------------------------------------------------------===//
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// asuint builtins
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//===----------------------------------------------------------------------===//
@@ -87,6 +116,7 @@ void asuint(double4, out uint4, out uint4);
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/// \fn uint16_t asuint16(T X)
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/// \brief Interprets the bit pattern of \a X as an 16-bit unsigned integer.
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/// \param X The input value.
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#ifdef __HLSL_ENABLE_16_BIT
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template <typename T, int N>

‎clang/test/CodeGenHLSL/builtins/asint16.hlsl

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// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple dxil-pc-shadermodel6.2-library %s -fnative-half-type -emit-llvm -O1 -o - | FileCheck %s
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//CHECK-LABEL: define {{.*}}test_ints
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//CHECK-SAME: {{.*}}(i16 {{.*}} [[VAL:%.*]]){{.*}}
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//CHECK-NOT: bitcast
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//CHECK: entry:
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//CHECK-NEXT: ret i16 [[VAL]]
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int16_t test_int(int16_t p0)
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{
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return asint16(p0);
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}
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//CHECK-LABEL: define {{.*}}test_uint
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//CHECK-SAME: {{.*}}(i16 {{.*}} [[VAL:%.*]]){{.*}}
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//CHECK-NOT:bitcast
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//CHECK: entry:
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//CHECK-NEXT: ret i16 [[VAL]]
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int16_t test_uint(uint16_t p0)
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{
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return asint16(p0);
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}
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//CHECK-LABEL: define {{.*}}test_half
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//CHECK-SAME: {{.*}}(half {{.*}} [[VAL:%.*]]){{.*}}
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//CHECK: [[RES:%.*]] = bitcast half [[VAL]] to i16
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//CHECK-NEXT : ret i16 [[RES]]
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int16_t test_half(half p0)
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{
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return asint16(p0);
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}
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//CHECK-LABEL: define {{.*}}test_vector_int
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//CHECK-SAME: {{.*}}(<4 x i16> {{.*}} [[VAL:%.*]]){{.*}}
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//CHECK-NOT: bitcast
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//CHECK: entry:
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//CHECK-NEXT: ret <4 x i16> [[VAL]]
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int16_t4 test_vector_int(int16_t4 p0)
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{
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return asint16(p0);
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}
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//CHECK-LABEL: define {{.*}}test_vector_uint
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//CHECK-SAME: {{.*}}(<4 x i16> {{.*}} [[VAL:%.*]]){{.*}}
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//CHECK-NOT: bitcast
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//CHECK-NEXT: entry:
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//CHECK-NEXT: ret <4 x i16> [[VAL]]
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int16_t4 test_vector_uint(uint16_t4 p0)
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{
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return asint16(p0);
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}
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//CHECK-LABEL: define {{.*}}fn
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//CHECK-SAME: {{.*}}(<4 x half> {{.*}} [[VAL:%.*]]){{.*}}
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//CHECK: [[RES:%.*]] = bitcast <4 x half> [[VAL]] to <4 x i16>
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//CHECK-NEXT: ret <4 x i16> [[RES]]
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int16_t4 fn(half4 p1)
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{
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return asint16(p1);
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}
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‎clang/test/SemaHLSL/BuiltIns/asint16-errors.hlsl

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// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.2-library %s -fnative-half-type -verify
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int16_t4 test_asint16_too_many_arg(uint16_t p0, uint16_t p1)
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{
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return asint16(p0, p1);
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// expected-error@-1 {{no matching function for call to 'asint16'}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate function template not viable: requires single argument 'V', but 2 arguments were provided}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate function template not viable: requires single argument 'F', but 2 arguments were provided}}
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}
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int16_t test_asint16_int(int p1)
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{
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return asint16(p1);
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// expected-error@-1 {{no matching function for call to 'asint16'}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate template ignored: could not match 'vector<T, N>' against 'int'}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate template ignored: substitution failure [with T = int]: no type named 'Type'}}
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}
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int16_t test_asint16_float(float p1)
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{
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return asint16(p1);
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// expected-error@-1 {{no matching function for call to 'asint16'}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate template ignored: could not match 'vector<T, N>' against 'float'}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate template ignored: substitution failure [with T = float]: no type named 'Type'}}
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}
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int16_t4 test_asint16_vector_int(int4 p1)
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{
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return asint16(p1);
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// expected-error@-1 {{no matching function for call to 'asint16'}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate template ignored: substitution failure [with T = int, N = 4]: no type named 'Type'}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate template ignored: substitution failure [with T = int4]: no type named 'Type'}}
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}
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int16_t4 test_asint16_vector_float(float4 p1)
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{
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return asint16(p1);
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// expected-error@-1 {{no matching function for call to 'asint16'}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate template ignored: substitution failure [with T = float, N = 4]: no type named 'Type'}}
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// expected-note@hlsl/hlsl_intrinsics.h:* {{candidate template ignored: substitution failure [with T = float4]: no type named 'Type'}}
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}
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‎llvm/test/CodeGen/SPIRV/bitcast.ll

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@@ -4,6 +4,7 @@
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; CHECK-SPIRV-DAG: %[[#TyInt32:]] = OpTypeInt 32 0
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; CHECK-SPIRV-DAG: %[[#TyInt16:]] = OpTypeInt 16 0
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; CHECK-SPIRV-DAG: %[[#TyHalf:]] = OpTypeFloat 16
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; CHECK-SPIRV-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#TyHalf]] 4
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; CHECK-SPIRV-DAG: %[[#Arg32:]] = OpFunctionParameter %[[#TyInt32]]
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; CHECK-SPIRV-DAG: %[[#Arg16:]] = OpUConvert %[[#TyInt16]] %[[#Arg32]]
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; CHECK-SPIRV-DAG: %[[#ValHalf:]] = OpBitcast %[[#TyHalf]] %[[#Arg16:]]
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%res = bitcast half %val2 to i16
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ret i16 %res
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}
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define <4 x i16> @test_vector_half4(<4 x half> nofpclass(nan inf) %p1) {
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entry:
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; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
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; CHECK: %[[#Res1:]] = OpBitcast %[[#vec4_int_16]] %[[#arg0]]
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%0 = bitcast <4 x half> %p1 to <4 x i16>
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; CHECK: OpReturnValue %[[#Res1]]
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ret <4 x i16> %0
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}

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