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nitinjohnrajnitinjohnraj
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[RISCV][GISel] Select G_SELECT
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‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

+29
Original file line numberDiff line numberDiff line change
@@ -44,11 +44,17 @@ class RISCVInstructionSelector : public InstructionSelector {
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const TargetRegisterClass *
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getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
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// tblgen-erated 'select' implementation, used as the initial selector for
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// the patterns that don't require complex C++.
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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// Custom selection methods
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bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
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bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB,
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MachineRegisterInfo &MRI) const;
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bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const;
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bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB,
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MachineRegisterInfo &MRI) const;
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bool earlySelectShift(unsigned Opc, MachineInstr &I, MachineIRBuilder &MIB,
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const MachineRegisterInfo &MRI);
@@ -240,6 +246,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
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}
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case TargetOpcode::G_SEXT_INREG:
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return selectSExtInreg(MI, MIB);
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case TargetOpcode::G_SELECT:
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return selectSelect(MI, MIB, MRI);
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default:
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return false;
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}
@@ -389,6 +397,27 @@ bool RISCVInstructionSelector::selectSExtInreg(MachineInstr &MI,
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return true;
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}
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bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
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MachineIRBuilder &MIB,
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MachineRegisterInfo &MRI) const {
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// TODO: Currently we check that the conditional code passed to G_SELECT is
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// not equal to zero; however, in the future, we might want to try and check
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// if the conditional code comes from a G_ICMP. If it does, we can directly
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// use G_ICMP to get the first three input operands of the
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// Select_GPR_Using_CC_GPR. This might be done here, or in the appropriate
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// combiner.
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assert(MI.getOpcode() == TargetOpcode::G_SELECT);
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MachineInstr *Result = MIB.buildInstr(RISCV::Select_GPR_Using_CC_GPR)
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.addDef(MI.getOperand(0).getReg())
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.addReg(MI.getOperand(1).getReg())
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.addReg(RISCV::X0)
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.addImm(RISCVCC::COND_NE)
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.addReg(MI.getOperand(2).getReg())
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.addReg(MI.getOperand(3).getReg());
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MI.eraseFromParent();
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return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI);
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}
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namespace llvm {
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InstructionSelector *
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createRISCVInstructionSelector(const RISCVTargetMachine &TM,

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir

+55
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=instruction-select --simplify-mir \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: select_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11, $x12
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; CHECK-LABEL: name: select_s32
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; CHECK: liveins: $x10, $x11, $x12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]]
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; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:gprb(s32) = COPY $x10
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%1:gprb(s32) = COPY $x11
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%2:gprb(s32) = COPY $x12
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%3:gprb(s32) = G_SELECT %0, %1, %2
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$x10 = COPY %3(s32)
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PseudoRET implicit $x10
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...
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---
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name: select_p0
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11, $x12
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; CHECK-LABEL: name: select_p0
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; CHECK: liveins: $x10, $x11, $x12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]]
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; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:gprb(s32) = COPY $x10
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%1:gprb(p0) = COPY $x11
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%2:gprb(p0) = COPY $x12
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%3:gprb(p0) = G_SELECT %0, %1, %2
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$x10 = COPY %3(p0)
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PseudoRET implicit $x10
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir

+55
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
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# RUN: | FileCheck %s
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---
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name: select_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11, $x12
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; CHECK-LABEL: name: select_s64
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; CHECK: liveins: $x10, $x11, $x12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]]
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; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s64) = COPY $x11
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%2:gprb(s64) = COPY $x12
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%3:gprb(s64) = G_SELECT %0, %1, %2
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$x10 = COPY %3(s64)
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PseudoRET implicit $x10
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29+
...
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---
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name: select_p0
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11, $x12
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39+
; CHECK-LABEL: name: select_p0
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; CHECK: liveins: $x10, $x11, $x12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]]
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; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(p0) = COPY $x11
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%2:gprb(p0) = COPY $x12
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%3:gprb(p0) = G_SELECT %0, %1, %2
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$x10 = COPY %3(p0)
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PseudoRET implicit $x10
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...

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