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[HLSL] Implement WaveActiveAllTrue Intrinsic
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‎clang/include/clang/Basic/Builtins.td

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@@ -4750,6 +4750,12 @@ def HLSLAny : LangBuiltin<"HLSL_LANG"> {
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let Prototype = "bool(...)";
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}
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def HLSLWaveActiveAllTrue : LangBuiltin<"HLSL_LANG"> {
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let Spellings = ["__builtin_hlsl_wave_active_all_true"];
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let Attributes = [NoThrow, Const];
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let Prototype = "bool(bool)";
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}
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def HLSLWaveActiveAnyTrue : LangBuiltin<"HLSL_LANG"> {
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let Spellings = ["__builtin_hlsl_wave_active_any_true"];
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let Attributes = [NoThrow, Const];

‎clang/lib/CodeGen/CGBuiltin.cpp

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@@ -19282,6 +19282,16 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
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/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
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ArrayRef<Value *>{Op0, Op1}, nullptr, "hlsl.step");
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}
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case Builtin::BI__builtin_hlsl_wave_active_all_true: {
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Value *Op = EmitScalarExpr(E->getArg(0));
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llvm::Type *Ty = Op->getType();
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assert(Ty->isIntegerTy(1) &&
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"Intrinsic WaveActiveAllTrue operand must be a bool");
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Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveAllTrueIntrinsic();
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return EmitRuntimeCall(
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Intrinsic::getOrInsertDeclaration(&CGM.getModule(), ID), {Op});
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}
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case Builtin::BI__builtin_hlsl_wave_active_any_true: {
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Value *Op = EmitScalarExpr(E->getArg(0));
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assert(Op->getType()->isIntegerTy(1) &&

‎clang/lib/CodeGen/CGHLSLRuntime.h

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@@ -91,6 +91,7 @@ class CGHLSLRuntime {
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GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
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GENERATE_HLSL_INTRINSIC_FUNCTION(Dot4AddI8Packed, dot4add_i8packed)
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GENERATE_HLSL_INTRINSIC_FUNCTION(Dot4AddU8Packed, dot4add_u8packed)
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GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveAllTrue, wave_all)
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GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveAnyTrue, wave_any)
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GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveCountBits, wave_active_countbits)
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GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)

‎clang/lib/Headers/hlsl/hlsl_intrinsics.h

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@@ -2223,6 +2223,15 @@ float4 trunc(float4);
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// Wave* builtins
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//===----------------------------------------------------------------------===//
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/// \brief Returns true if the expression is true in all active lanes in the
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/// current wave.
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///
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/// \param Val The boolean expression to evaluate.
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/// \return True if the expression is true in all lanes.
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_HLSL_AVAILABILITY(shadermodel, 6.0)
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_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_all_true)
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__attribute__((convergent)) bool WaveActiveAllTrue(bool Val);
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/// \brief Returns true if the expression is true in any active lane in the
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/// current wave.
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///

‎clang/test/CodeGenHLSL/builtins/WaveActiveAllTrue.hlsl

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@@ -0,0 +1,17 @@
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// RUN: %clang_cc1 -finclude-default-header -fnative-half-type -triple \
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// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \
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// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
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// RUN: %clang_cc1 -finclude-default-header -fnative-half-type -triple \
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// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \
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// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV
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// Test basic lowering to runtime function call for int values.
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// CHECK-LABEL: define {{.*}}test
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bool test(bool p1) {
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// CHECK-SPIRV: %[[#entry_tok0:]] = call token @llvm.experimental.convergence.entry()
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// CHECK-SPIRV: %[[RET:.*]] = call spir_func i1 @llvm.spv.wave.all(i1 %{{[a-zA-Z0-9]+}}) [ "convergencectrl"(token %[[#entry_tok0]]) ]
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// CHECK-DXIL: %[[RET:.*]] = call i1 @llvm.dx.wave.all(i1 %{{[a-zA-Z0-9]+}})
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// CHECK: ret i1 %[[RET]]
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return WaveActiveAllTrue(p1);
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}

‎clang/test/SemaHLSL/BuiltIns/WaveActiveAllTrue-errors.hlsl

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@@ -0,0 +1,21 @@
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// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify
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bool test_too_few_arg() {
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return __builtin_hlsl_wave_active_all_true();
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// expected-error@-1 {{too few arguments to function call, expected 1, have 0}}
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}
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bool test_too_many_arg(bool p0) {
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return __builtin_hlsl_wave_active_all_true(p0, p0);
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// expected-error@-1 {{too many arguments to function call, expected 1, have 2}}
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}
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struct Foo
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{
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int a;
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};
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bool test_type_check(Foo p0) {
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return __builtin_hlsl_wave_active_all_true(p0);
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// expected-error@-1 {{no viable conversion from 'Foo' to 'bool'}}
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}

‎llvm/include/llvm/IR/IntrinsicsDirectX.td

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@@ -94,6 +94,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV
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def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
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def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
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def int_dx_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
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def int_dx_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
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def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent, IntrNoMem]>;
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def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;

‎llvm/include/llvm/IR/IntrinsicsSPIRV.td

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@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
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def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_spv_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
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def int_spv_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
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def int_spv_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
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def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
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def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;

‎llvm/lib/Target/DirectX/DXIL.td

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@@ -861,6 +861,14 @@ def CreateHandleFromBinding : DXILOp<217, createHandleFromBinding> {
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let stages = [Stages<DXIL1_6, [all_stages]>];
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}
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def WaveActiveAllTrue : DXILOp<334, waveAllTrue> {
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let Doc = "returns true if the expression is true in all of the active lanes in the current wave";
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let LLVMIntrinsic = int_dx_wave_all;
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let arguments = [Int1Ty];
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let result = Int1Ty;
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let stages = [Stages<DXIL1_0, [all_stages]>];
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}
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def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
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let Doc = "returns true if the expression is true in any of the active lanes in the current wave";
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let LLVMIntrinsic = int_dx_wave_any;

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

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@@ -2830,6 +2830,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
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return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
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case Intrinsic::spv_wave_active_countbits:
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return selectWaveActiveCountBits(ResVReg, ResType, I);
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case Intrinsic::spv_wave_all:
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return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAll);
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case Intrinsic::spv_wave_any:
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return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny);
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case Intrinsic::spv_wave_is_first_lane:

‎llvm/test/CodeGen/DirectX/WaveActiveAllTrue.ll

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@@ -0,0 +1,10 @@
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; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s
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define noundef i1 @wave_all_simple(i1 noundef %p1) {
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entry:
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; CHECK: call i1 @dx.op.waveAllTrue(i32 334, i1 %p1)
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%ret = call i1 @llvm.dx.wave.all(i1 %p1)
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ret i1 %ret
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}
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declare i1 @llvm.dx.wave.all(i1)

‎llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAllTrue.ll

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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: %[[#bool:]] = OpTypeBool
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; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0
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; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 3
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; CHECK-DAG: OpCapability GroupNonUniformVote
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; CHECK-LABEL: Begin function test_wave_all
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define i1 @test_wave_all(i1 %p1) #0 {
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entry:
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; CHECK: %[[#param:]] = OpFunctionParameter %[[#bool]]
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; CHECK: %{{.+}} = OpGroupNonUniformAll %[[#bool]] %[[#scope]] %[[#param]]
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%0 = call token @llvm.experimental.convergence.entry()
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%ret = call i1 @llvm.spv.wave.all(i1 %p1) [ "convergencectrl"(token %0) ]
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ret i1 %ret
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}
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declare i1 @llvm.spv.wave.all(i1) #0
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attributes #0 = { convergent }

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