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[RISCV] Make M imply Zmmul (#95070)
According to the spec, M implies Zmmul.
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17 files changed

+101
-94
lines changed

17 files changed

+101
-94
lines changed

‎clang/lib/Basic/Targets/RISCV.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
168168
Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor)));
169169
}
170170

171-
if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul"))
171+
if (ISAInfo->hasExtension("zmmul"))
172172
Builder.defineMacro("__riscv_mul");
173173

174174
if (ISAInfo->hasExtension("m")) {

‎clang/test/CodeGen/RISCV/riscv-func-attr-target.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -66,16 +66,16 @@ void test_rvv_f64_type_w_zve64d() {
6666
}
6767

6868
//.
69-
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" }
70-
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
71-
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
72-
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
69+
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa" }
70+
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
71+
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" }
72+
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
7373
// Make sure we append negative features if we override the arch
74-
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
75-
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
76-
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
77-
// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
78-
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
79-
// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
80-
// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
81-
// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }
74+
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
75+
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
76+
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" }
77+
// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
78+
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
79+
// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
80+
// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
81+
// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }

‎lld/test/ELF/lto/riscv-attributes.ll‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,10 @@
1010
; CHECK: BuildAttributes {
1111
; CHECK-NEXT: FormatVersion: 0x41
1212
; CHECK-NEXT: Section 1 {
13-
; CHECK-NEXT: SectionLength: 70
13+
; CHECK-NEXT: SectionLength: 79
1414
; CHECK-NEXT: Vendor: riscv
1515
; CHECK-NEXT: Tag: Tag_File (0x1)
16-
; CHECK-NEXT: Size: 60
16+
; CHECK-NEXT: Size: 69
1717
; CHECK-NEXT: FileAttributes {
1818
; CHECK-NEXT: Attribute {
1919
; CHECK-NEXT: Tag: 4
@@ -30,18 +30,18 @@
3030
; CHECK-NEXT: Attribute {
3131
; CHECK-NEXT: Tag: 5
3232
; CHECK-NEXT: TagName: arch
33-
; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zbb1p0{{$}}
33+
; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zbb1p0{{$}}
3434
; CHECK-NEXT: }
3535
; CHECK-NEXT: }
3636
; CHECK-NEXT: }
3737
; CHECK-NEXT: }
3838

3939
;--- 1.s
4040
.attribute 4, 16
41-
.attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
41+
.attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zmmul1p0"
4242
;--- 2.s
4343
.attribute 4, 16
44-
.attribute 5, "rv32i2p1_m2p0_f2p2_d2p2_zbb1p0"
44+
.attribute 5, "rv32i2p1_m2p0_f2p2_d2p2_zbb1p0_zmmul1p0"
4545
.attribute 6, 1
4646

4747
;--- a.ll

‎lld/test/ELF/riscv-attributes.s‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -64,20 +64,20 @@
6464
# UNKNOWN22: warning: unknown22a.o:(.riscv.attributes): invalid tag 0x16 at offset 0x10
6565

6666
# HDR: Name Type Address Off Size ES Flg Lk Inf Al
67-
# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 00003e 00 0 0 1{{$}}
67+
# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 000047 00 0 0 1{{$}}
6868

6969
# HDR: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
7070
# HDR: LOAD 0x000000 0x0000000000010000 0x0000000000010000 0x000158 0x000158 R 0x1000
7171
# HDR-NEXT: GNU_STACK 0x000000 0x0000000000000000 0x0000000000000000 0x000000 0x000000 RW 0
72-
# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x00003e 0x00003e R 0x1{{$}}
72+
# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x000047 0x000047 R 0x1{{$}}
7373

7474
# CHECK: BuildAttributes {
7575
# CHECK-NEXT: FormatVersion: 0x41
7676
# CHECK-NEXT: Section 1 {
77-
# CHECK-NEXT: SectionLength: 61
77+
# CHECK-NEXT: SectionLength: 70
7878
# CHECK-NEXT: Vendor: riscv
7979
# CHECK-NEXT: Tag: Tag_File (0x1)
80-
# CHECK-NEXT: Size: 51
80+
# CHECK-NEXT: Size: 60
8181
# CHECK-NEXT: FileAttributes {
8282
# CHECK-NEXT: Attribute {
8383
# CHECK-NEXT: Tag: 4
@@ -88,7 +88,7 @@
8888
# CHECK-NEXT: Attribute {
8989
# CHECK-NEXT: Tag: 5
9090
# CHECK-NEXT: TagName: arch
91-
# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0{{$}}
91+
# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0{{$}}
9292
# CHECK-NEXT: }
9393
# CHECK-NEXT: }
9494
# CHECK-NEXT: }
@@ -97,10 +97,10 @@
9797
# CHECK2: BuildAttributes {
9898
# CHECK2-NEXT: FormatVersion: 0x41
9999
# CHECK2-NEXT: Section 1 {
100-
# CHECK2-NEXT: SectionLength: 104
100+
# CHECK2-NEXT: SectionLength: 113
101101
# CHECK2-NEXT: Vendor: riscv
102102
# CHECK2-NEXT: Tag: Tag_File (0x1)
103-
# CHECK2-NEXT: Size: 94
103+
# CHECK2-NEXT: Size: 103
104104
# CHECK2-NEXT: FileAttributes {
105105
# CHECK2-NEXT: Attribute {
106106
# CHECK2-NEXT: Tag: 4
@@ -127,7 +127,7 @@
127127
# CHECK2-NEXT: Attribute {
128128
# CHECK2-NEXT: Tag: 5
129129
# CHECK2-NEXT: TagName: arch
130-
# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}}
130+
# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}}
131131
# CHECK2-NEXT: }
132132
# CHECK2-NEXT: }
133133
# CHECK2-NEXT: }
@@ -152,12 +152,12 @@
152152

153153
#--- a.s
154154
.attribute stack_align, 16
155-
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
155+
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zmmul1p0"
156156
.attribute unaligned_access, 0
157157

158158
#--- b.s
159159
.attribute stack_align, 16
160-
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
160+
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zmmul1p0"
161161
.attribute priv_spec, 2
162162
.attribute priv_spec_minor, 2
163163

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -305,7 +305,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
305305
getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE, G_CONSTANT_POOL})
306306
.legalFor({p0});
307307

308-
if (ST.hasStdExtM() || ST.hasStdExtZmmul()) {
308+
if (ST.hasStdExtZmmul()) {
309309
getActionDefinitionsBuilder(G_MUL)
310310
.legalFor({s32, sXLen})
311311
.widenScalarToNextPow2(0)

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -171,23 +171,21 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
171171

172172
// Multiply Extensions
173173

174+
def FeatureStdExtZmmul
175+
: RISCVExtension<"zmmul", 1, 0,
176+
"'Zmmul' (Integer Multiplication)">;
177+
def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,
178+
AssemblerPredicate<(all_of FeatureStdExtZmmul),
179+
"'Zmmul' (Integer Multiplication)">;
180+
174181
def FeatureStdExtM
175182
: RISCVExtension<"m", 2, 0,
176-
"'M' (Integer Multiplication and Division)">;
183+
"'M' (Integer Multiplication and Division)",
184+
[FeatureStdExtZmmul]>;
177185
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
178186
AssemblerPredicate<(all_of FeatureStdExtM),
179187
"'M' (Integer Multiplication and Division)">;
180188

181-
def FeatureStdExtZmmul
182-
: RISCVExtension<"zmmul", 1, 0,
183-
"'Zmmul' (Integer Multiplication)">;
184-
185-
def HasStdExtMOrZmmul
186-
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
187-
AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul),
188-
"'M' (Integer Multiplication and Division) or "
189-
"'Zmmul' (Integer Multiplication)">;
190-
191189
// Atomic Extensions
192190

193191
def FeatureStdExtA

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
300300
setLibcallName(RTLIB::MULO_I64, nullptr);
301301
}
302302

303-
if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul()) {
303+
if (!Subtarget.hasStdExtZmmul()) {
304304
setOperationAction({ISD::MUL, ISD::MULHS, ISD::MULHU}, XLenVT, Expand);
305305
if (RV64LegalI32 && Subtarget.is64Bit())
306306
setOperationAction(ISD::MUL, MVT::i32, Promote);
@@ -21144,14 +21144,13 @@ bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned)
2114421144
bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
2114521145
SDValue C) const {
2114621146
// Check integral scalar types.
21147-
const bool HasExtMOrZmmul =
21148-
Subtarget.hasStdExtM() || Subtarget.hasStdExtZmmul();
21147+
const bool HasZmmul = Subtarget.hasStdExtZmmul();
2114921148
if (!VT.isScalarInteger())
2115021149
return false;
2115121150

2115221151
// Omit the optimization if the sub target has the M extension and the data
2115321152
// size exceeds XLen.
21154-
if (HasExtMOrZmmul && VT.getSizeInBits() > Subtarget.getXLen())
21153+
if (HasZmmul && VT.getSizeInBits() > Subtarget.getXLen())
2115521154
return false;
2115621155

2115721156
if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3695,7 +3695,7 @@ void RISCVInstrInfo::mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
36953695
.addReg(ScaledRegister, RegState::Kill)
36963696
.addReg(DestReg, RegState::Kill)
36973697
.setMIFlag(Flag);
3698-
} else if (STI.hasStdExtM() || STI.hasStdExtZmmul()) {
3698+
} else if (STI.hasStdExtZmmul()) {
36993699
Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass);
37003700
movImm(MBB, II, DL, N, Amount, Flag);
37013701
BuildMI(MBB, II, DL, get(RISCV::MUL), DestReg)

‎llvm/lib/Target/RISCV/RISCVInstrInfoM.td‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ def riscv_remuw : SDNode<"RISCVISD::REMUW", SDT_RISCVIntBinOpW>;
2424
// Instructions
2525
//===----------------------------------------------------------------------===//
2626

27-
let Predicates = [HasStdExtMOrZmmul] in {
27+
let Predicates = [HasStdExtZmmul] in {
2828
def MUL : ALU_rr<0b0000001, 0b000, "mul", Commutable=1>,
2929
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
3030
def MULH : ALU_rr<0b0000001, 0b001, "mulh", Commutable=1>,
@@ -33,7 +33,7 @@ def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">,
3333
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
3434
def MULHU : ALU_rr<0b0000001, 0b011, "mulhu", Commutable=1>,
3535
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
36-
} // Predicates = [HasStdExtMOrZmmul]
36+
} // Predicates = [HasStdExtZmmul]
3737

3838
let Predicates = [HasStdExtM] in {
3939
def DIV : ALU_rr<0b0000001, 0b100, "div">,
@@ -46,10 +46,10 @@ def REMU : ALU_rr<0b0000001, 0b111, "remu">,
4646
Sched<[WriteIRem, ReadIRem, ReadIRem]>;
4747
} // Predicates = [HasStdExtM]
4848

49-
let Predicates = [HasStdExtMOrZmmul, IsRV64], IsSignExtendingOpW = 1 in {
49+
let Predicates = [HasStdExtZmmul, IsRV64], IsSignExtendingOpW = 1 in {
5050
def MULW : ALUW_rr<0b0000001, 0b000, "mulw", Commutable=1>,
5151
Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
52-
} // Predicates = [HasStdExtMOrZmmul, IsRV64]
52+
} // Predicates = [HasStdExtZmmul, IsRV64]
5353

5454
let Predicates = [HasStdExtM, IsRV64], IsSignExtendingOpW = 1 in {
5555
def DIVW : ALUW_rr<0b0000001, 0b100, "divw">,
@@ -66,12 +66,12 @@ def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">,
6666
// Pseudo-instructions and codegen patterns
6767
//===----------------------------------------------------------------------===//
6868

69-
let Predicates = [HasStdExtMOrZmmul] in {
69+
let Predicates = [HasStdExtZmmul] in {
7070
def : PatGprGpr<mul, MUL>;
7171
def : PatGprGpr<mulhs, MULH>;
7272
def : PatGprGpr<mulhu, MULHU>;
7373
def : PatGprGpr<riscv_mulhsu, MULHSU>;
74-
} // Predicates = [HasStdExtMOrZmmul]
74+
} // Predicates = [HasStdExtZmmul]
7575

7676
let Predicates = [HasStdExtM] in {
7777
def : PatGprGpr<sdiv, DIV>;
@@ -81,7 +81,7 @@ def : PatGprGpr<urem, REMU>;
8181
} // Predicates = [HasStdExtM]
8282

8383
// Select W instructions if only the lower 32-bits of the result are used.
84-
let Predicates = [HasStdExtMOrZmmul, IsRV64] in
84+
let Predicates = [HasStdExtZmmul, IsRV64] in
8585
def : PatGprGpr<binop_allwusers<mul>, MULW>;
8686

8787
let Predicates = [HasStdExtM, IsRV64] in {
@@ -106,20 +106,20 @@ def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
106106
(REMW GPR:$rs1, GPR:$rs2)>;
107107
} // Predicates = [HasStdExtM, IsRV64]
108108

109-
let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in {
109+
let Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] in {
110110
// Special case for calculating the full 64-bit product of a 32x32 unsigned
111111
// multiply where the inputs aren't known to be zero extended. We can shift the
112112
// inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
113113
// zeroing the upper 32 bits.
114114
def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
115115
(MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
116-
} // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba]
116+
} // Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba]
117117

118118
//===----------------------------------------------------------------------===//
119119
// Experimental RV64 i32 legalization patterns.
120120
//===----------------------------------------------------------------------===//
121121

122-
let Predicates = [HasStdExtMOrZmmul, IsRV64] in {
122+
let Predicates = [HasStdExtZmmul, IsRV64] in {
123123
def : PatGprGpr<mul, MULW, i32, i32>;
124124
}
125125

‎llvm/lib/Target/RISCV/RISCVInstrInfoZc.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -183,7 +183,7 @@ let Predicates = [HasStdExtZcb] in
183183
def C_ZEXT_B : RVZcArith_r<0b11000 , "c.zext.b">,
184184
Sched<[WriteIALU, ReadIALU]>;
185185

186-
let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in
186+
let Predicates = [HasStdExtZcb, HasStdExtZmmul] in
187187
def C_MUL : CA_ALU<0b100111, 0b10, "c.mul", GPRC>,
188188
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
189189

@@ -270,13 +270,13 @@ def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8ge32:$index),
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} // DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt]...
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273-
let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in{
273+
let Predicates = [HasStdExtZcb, HasStdExtZmmul] in{
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def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
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(C_MUL GPRC:$rs1, GPRC:$rs2)>;
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let isCompressOnly = true in
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def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
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(C_MUL GPRC:$rs1, GPRC:$rs2)>;
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} // Predicates = [HasStdExtZcb, HasStdExtMOrZmmul]
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} // Predicates = [HasStdExtZcb, HasStdExtZmmul]
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let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
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def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1),

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