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[AArch64][GlobalISel] Select SHL(ZEXT, DUP imm) into {U/S}HLL imm
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7996,6 +7996,20 @@ def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
79967996
(SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
79977997
V128:$Rn, vecshiftR32Narrow:$imm)>;
79987998

7999+
def : Pat<(shl (v8i16 (zext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm:$size)))),
8000+
(USHLLv8i8_shift V64:$Rm, (i32 imm:$size))>;
8001+
def : Pat<(shl (v4i32 (zext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm:$size)))),
8002+
(USHLLv4i16_shift V64:$Rm, (i32 imm:$size))>;
8003+
def : Pat<(shl (v2i64 (zext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm:$size)))),
8004+
(USHLLv2i32_shift V64:$Rm, (trunc_imm imm:$size))>;
8005+
8006+
def : Pat<(shl (v8i16 (sext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm:$size)))),
8007+
(SSHLLv8i8_shift V64:$Rm, (i32 imm:$size))>;
8008+
def : Pat<(shl (v4i32 (sext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm:$size)))),
8009+
(SSHLLv4i16_shift V64:$Rm, (i32 imm:$size))>;
8010+
def : Pat<(shl (v2i64 (sext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm:$size)))),
8011+
(SSHLLv2i32_shift V64:$Rm, (trunc_imm imm:$size))>;
8012+
79998013
// Vector sign and zero extensions are implemented with SSHLL and USSHLL.
80008014
// Anyexts are implemented as zexts.
80018015
def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;

‎llvm/test/CodeGen/AArch64/neon-shift-left-long.ll

Lines changed: 36 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -3,96 +3,60 @@
33
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
define <8 x i16> @test_sshll_v8i8(<8 x i8> %a) {
6-
; CHECK-SD-LABEL: test_sshll_v8i8:
7-
; CHECK-SD: // %bb.0:
8-
; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #3
9-
; CHECK-SD-NEXT: ret
10-
;
11-
; CHECK-GI-LABEL: test_sshll_v8i8:
12-
; CHECK-GI: // %bb.0:
13-
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
14-
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
15-
; CHECK-GI-NEXT: ret
6+
; CHECK-LABEL: test_sshll_v8i8:
7+
; CHECK: // %bb.0:
8+
; CHECK-NEXT: sshll v0.8h, v0.8b, #3
9+
; CHECK-NEXT: ret
1610
%1 = sext <8 x i8> %a to <8 x i16>
1711
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
1812
ret <8 x i16> %tmp
1913
}
2014

2115
define <4 x i32> @test_sshll_v4i16(<4 x i16> %a) {
22-
; CHECK-SD-LABEL: test_sshll_v4i16:
23-
; CHECK-SD: // %bb.0:
24-
; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #9
25-
; CHECK-SD-NEXT: ret
26-
;
27-
; CHECK-GI-LABEL: test_sshll_v4i16:
28-
; CHECK-GI: // %bb.0:
29-
; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0
30-
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
31-
; CHECK-GI-NEXT: ret
16+
; CHECK-LABEL: test_sshll_v4i16:
17+
; CHECK: // %bb.0:
18+
; CHECK-NEXT: sshll v0.4s, v0.4h, #9
19+
; CHECK-NEXT: ret
3220
%1 = sext <4 x i16> %a to <4 x i32>
3321
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
3422
ret <4 x i32> %tmp
3523
}
3624

3725
define <2 x i64> @test_sshll_v2i32(<2 x i32> %a) {
38-
; CHECK-SD-LABEL: test_sshll_v2i32:
39-
; CHECK-SD: // %bb.0:
40-
; CHECK-SD-NEXT: sshll v0.2d, v0.2s, #19
41-
; CHECK-SD-NEXT: ret
42-
;
43-
; CHECK-GI-LABEL: test_sshll_v2i32:
44-
; CHECK-GI: // %bb.0:
45-
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
46-
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
47-
; CHECK-GI-NEXT: ret
26+
; CHECK-LABEL: test_sshll_v2i32:
27+
; CHECK: // %bb.0:
28+
; CHECK-NEXT: sshll v0.2d, v0.2s, #19
29+
; CHECK-NEXT: ret
4830
%1 = sext <2 x i32> %a to <2 x i64>
4931
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
5032
ret <2 x i64> %tmp
5133
}
5234

5335
define <8 x i16> @test_ushll_v8i8(<8 x i8> %a) {
54-
; CHECK-SD-LABEL: test_ushll_v8i8:
55-
; CHECK-SD: // %bb.0:
56-
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #3
57-
; CHECK-SD-NEXT: ret
58-
;
59-
; CHECK-GI-LABEL: test_ushll_v8i8:
60-
; CHECK-GI: // %bb.0:
61-
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
62-
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
63-
; CHECK-GI-NEXT: ret
36+
; CHECK-LABEL: test_ushll_v8i8:
37+
; CHECK: // %bb.0:
38+
; CHECK-NEXT: ushll v0.8h, v0.8b, #3
39+
; CHECK-NEXT: ret
6440
%1 = zext <8 x i8> %a to <8 x i16>
6541
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
6642
ret <8 x i16> %tmp
6743
}
6844

6945
define <4 x i32> @test_ushll_v4i16(<4 x i16> %a) {
70-
; CHECK-SD-LABEL: test_ushll_v4i16:
71-
; CHECK-SD: // %bb.0:
72-
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #9
73-
; CHECK-SD-NEXT: ret
74-
;
75-
; CHECK-GI-LABEL: test_ushll_v4i16:
76-
; CHECK-GI: // %bb.0:
77-
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
78-
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
79-
; CHECK-GI-NEXT: ret
46+
; CHECK-LABEL: test_ushll_v4i16:
47+
; CHECK: // %bb.0:
48+
; CHECK-NEXT: ushll v0.4s, v0.4h, #9
49+
; CHECK-NEXT: ret
8050
%1 = zext <4 x i16> %a to <4 x i32>
8151
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
8252
ret <4 x i32> %tmp
8353
}
8454

8555
define <2 x i64> @test_ushll_v2i32(<2 x i32> %a) {
86-
; CHECK-SD-LABEL: test_ushll_v2i32:
87-
; CHECK-SD: // %bb.0:
88-
; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #19
89-
; CHECK-SD-NEXT: ret
90-
;
91-
; CHECK-GI-LABEL: test_ushll_v2i32:
92-
; CHECK-GI: // %bb.0:
93-
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
94-
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
95-
; CHECK-GI-NEXT: ret
56+
; CHECK-LABEL: test_ushll_v2i32:
57+
; CHECK: // %bb.0:
58+
; CHECK-NEXT: ushll v0.2d, v0.2s, #19
59+
; CHECK-NEXT: ret
9660
%1 = zext <2 x i32> %a to <2 x i64>
9761
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
9862
ret <2 x i64> %tmp
@@ -106,8 +70,8 @@ define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {
10670
;
10771
; CHECK-GI-LABEL: test_sshll2_v16i8:
10872
; CHECK-GI: // %bb.0:
109-
; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
110-
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
73+
; CHECK-GI-NEXT: mov d0, v0.d[1]
74+
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #3
11175
; CHECK-GI-NEXT: ret
11276
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
11377
%2 = sext <8 x i8> %1 to <8 x i16>
@@ -123,8 +87,8 @@ define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {
12387
;
12488
; CHECK-GI-LABEL: test_sshll2_v8i16:
12589
; CHECK-GI: // %bb.0:
126-
; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
127-
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
90+
; CHECK-GI-NEXT: mov d0, v0.d[1]
91+
; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #9
12892
; CHECK-GI-NEXT: ret
12993
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
13094
%2 = sext <4 x i16> %1 to <4 x i32>
@@ -140,8 +104,8 @@ define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {
140104
;
141105
; CHECK-GI-LABEL: test_sshll2_v4i32:
142106
; CHECK-GI: // %bb.0:
143-
; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0
144-
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
107+
; CHECK-GI-NEXT: mov d0, v0.d[1]
108+
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #19
145109
; CHECK-GI-NEXT: ret
146110
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
147111
%2 = sext <2 x i32> %1 to <2 x i64>
@@ -157,8 +121,8 @@ define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {
157121
;
158122
; CHECK-GI-LABEL: test_ushll2_v16i8:
159123
; CHECK-GI: // %bb.0:
160-
; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
161-
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
124+
; CHECK-GI-NEXT: mov d0, v0.d[1]
125+
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #3
162126
; CHECK-GI-NEXT: ret
163127
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
164128
%2 = zext <8 x i8> %1 to <8 x i16>
@@ -174,8 +138,8 @@ define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {
174138
;
175139
; CHECK-GI-LABEL: test_ushll2_v8i16:
176140
; CHECK-GI: // %bb.0:
177-
; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
178-
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
141+
; CHECK-GI-NEXT: mov d0, v0.d[1]
142+
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #9
179143
; CHECK-GI-NEXT: ret
180144
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
181145
%2 = zext <4 x i16> %1 to <4 x i32>
@@ -191,8 +155,8 @@ define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {
191155
;
192156
; CHECK-GI-LABEL: test_ushll2_v4i32:
193157
; CHECK-GI: // %bb.0:
194-
; CHECK-GI-NEXT: ushll2 v0.2d, v0.4s, #0
195-
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
158+
; CHECK-GI-NEXT: mov d0, v0.d[1]
159+
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #19
196160
; CHECK-GI-NEXT: ret
197161
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
198162
%2 = zext <2 x i32> %1 to <2 x i64>

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