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[AMDGPU][AsmParser][NFC] Translate parsed MIMG instructions to MCInsts automatically.
Part of <#62629>. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D155061
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 1 addition & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -1738,10 +1738,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17381738

17391739
void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
17401740
void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);
1741-
1742-
void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
1743-
bool IsAtomic = false);
1744-
void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
17451741
void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands);
17461742

17471743
bool parseDimId(unsigned &Encoding);
@@ -7654,60 +7650,9 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
76547650
}
76557651

76567652
//===----------------------------------------------------------------------===//
7657-
// mimg
7653+
// SMEM
76587654
//===----------------------------------------------------------------------===//
76597655

7660-
void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands,
7661-
bool IsAtomic) {
7662-
unsigned I = 1;
7663-
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
7664-
for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
7665-
((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
7666-
}
7667-
7668-
if (IsAtomic) {
7669-
// Add src, same as dst
7670-
assert(Desc.getNumDefs() == 1);
7671-
((AMDGPUOperand &)*Operands[I - 1]).addRegOperands(Inst, 1);
7672-
}
7673-
7674-
OptionalImmIndexMap OptionalIdx;
7675-
7676-
for (unsigned E = Operands.size(); I != E; ++I) {
7677-
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
7678-
7679-
// Add the register arguments
7680-
if (Op.isReg()) {
7681-
Op.addRegOperands(Inst, 1);
7682-
} else if (Op.isImmModifier()) {
7683-
OptionalIdx[Op.getImmTy()] = I;
7684-
} else if (!Op.isToken()) {
7685-
llvm_unreachable("unexpected operand type");
7686-
}
7687-
}
7688-
7689-
bool IsGFX10Plus = isGFX10Plus();
7690-
7691-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
7692-
if (IsGFX10Plus)
7693-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDim, -1);
7694-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
7695-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol);
7696-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16);
7697-
if (IsGFX10Plus)
7698-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyA16);
7699-
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::tfe))
7700-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
7701-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
7702-
if (!IsGFX10Plus)
7703-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
7704-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyD16);
7705-
}
7706-
7707-
void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {
7708-
cvtMIMG(Inst, Operands, true);
7709-
}
7710-
77117656
void AMDGPUAsmParser::cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands) {
77127657
OptionalImmIndexMap OptionalIdx;
77137658
bool IsAtomicReturn = false;

‎llvm/lib/Target/AMDGPU/MIMGInstructions.td

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -207,7 +207,6 @@ class MIMG <dag outs, string dns = "">
207207
: MIMG_Base <outs, dns> {
208208

209209
let hasPostISelHook = 1;
210-
let AsmMatchConverter = "cvtMIMG";
211210

212211
Instruction Opcode = !cast<Instruction>(NAME);
213212
MIMGBaseOpcode BaseOpcode;
@@ -693,7 +692,6 @@ class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
693692
RegisterClass addr_rc, string dns="">
694693
: MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
695694
let Constraints = "$vdst = $vdata";
696-
let AsmMatchConverter = "cvtMIMGAtomic";
697695

698696
let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
699697
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
@@ -705,7 +703,6 @@ class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc,
705703
RegisterClass addr_rc, string dns="">
706704
: MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> {
707705
let Constraints = "$vdst = $vdata";
708-
let AsmMatchConverter = "cvtMIMGAtomic";
709706

710707
let InOperandList = (ins getLdStRegisterOperand<data_rc>.ret:$vdata,
711708
addr_rc:$vaddr, SReg_256:$srsrc,
@@ -741,7 +738,6 @@ class MIMG_Atomic_gfx10<mimgopc op, string opcode,
741738
: MIMG_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst),
742739
!if(enableDisasm, "AMDGPU", "")> {
743740
let Constraints = "$vdst = $vdata";
744-
let AsmMatchConverter = "cvtMIMGAtomic";
745741

746742
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
747743
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
@@ -755,7 +751,6 @@ class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode,
755751
: MIMG_nsa_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst), num_addrs,
756752
!if(enableDisasm, "AMDGPU", "")> {
757753
let Constraints = "$vdst = $vdata";
758-
let AsmMatchConverter = "cvtMIMGAtomic";
759754

760755
let InOperandList = !con((ins DataRC:$vdata),
761756
AddrIns,
@@ -771,7 +766,6 @@ class MIMG_Atomic_gfx11<mimgopc op, string opcode,
771766
: MIMG_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst),
772767
!if(enableDisasm, "AMDGPU", "")> {
773768
let Constraints = "$vdst = $vdata";
774-
let AsmMatchConverter = "cvtMIMGAtomic";
775769

776770
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
777771
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
@@ -785,7 +779,6 @@ class MIMG_Atomic_nsa_gfx11<mimgopc op, string opcode,
785779
: MIMG_nsa_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst), num_addrs,
786780
!if(enableDisasm, "AMDGPU", "")> {
787781
let Constraints = "$vdst = $vdata";
788-
let AsmMatchConverter = "cvtMIMGAtomic";
789782

790783
let InOperandList = !con((ins DataRC:$vdata),
791784
AddrIns,
@@ -1228,8 +1221,7 @@ multiclass MIMG_IntersectRay<mimgopc op, string opcode, bit Is64, bit IsA16> {
12281221
let BVH = 1;
12291222
let A16 = IsA16;
12301223
}
1231-
let AsmMatchConverter = "",
1232-
dmask = 0xf,
1224+
let dmask = 0xf,
12331225
unorm = 1,
12341226
d16 = 0,
12351227
cpol = 0,

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