@@ -11112,31 +11112,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
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}
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}
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- /// Given an integer binary operator, return the generic ISD::VECREDUCE_OP
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- /// which corresponds to it.
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- static unsigned getVecReduceOpcode(unsigned Opc) {
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- switch (Opc) {
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- default:
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- llvm_unreachable("Unhandled binary to transfrom reduction");
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- case ISD::ADD:
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- return ISD::VECREDUCE_ADD;
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- case ISD::UMAX:
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- return ISD::VECREDUCE_UMAX;
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- case ISD::SMAX:
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- return ISD::VECREDUCE_SMAX;
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- case ISD::UMIN:
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- return ISD::VECREDUCE_UMIN;
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- case ISD::SMIN:
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- return ISD::VECREDUCE_SMIN;
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- case ISD::AND:
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- return ISD::VECREDUCE_AND;
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- case ISD::OR:
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- return ISD::VECREDUCE_OR;
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- case ISD::XOR:
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- return ISD::VECREDUCE_XOR;
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- }
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- }
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-
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/// Perform two related transforms whose purpose is to incrementally recognize
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/// an explode_vector followed by scalar reduction as a vector reduction node.
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/// This exists to recover from a deficiency in SLP which can't handle
@@ -11155,15 +11130,8 @@ combineBinOpOfExtractToReduceTree(SDNode *N, SelectionDAG &DAG,
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const SDLoc DL(N);
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const EVT VT = N->getValueType(0);
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-
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- // TODO: Handle floating point here.
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- if (!VT.isInteger())
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- return SDValue();
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-
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- const unsigned Opc = N->getOpcode();
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- const unsigned ReduceOpc = getVecReduceOpcode(Opc);
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- assert(Opc == ISD::getVecReduceBaseOpcode(ReduceOpc) &&
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- "Inconsistent mappings");
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+ [[maybe_unused]] const unsigned Opc = N->getOpcode();
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+ assert(Opc == ISD::ADD && "extend this to other reduction types");
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const SDValue LHS = N->getOperand(0);
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const SDValue RHS = N->getOperand(1);
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@@ -11193,13 +11161,13 @@ combineBinOpOfExtractToReduceTree(SDNode *N, SelectionDAG &DAG,
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EVT ReduceVT = EVT::getVectorVT(*DAG.getContext(), VT, 2);
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SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec,
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DAG.getVectorIdxConstant(0, DL));
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- return DAG.getNode(ReduceOpc , DL, VT, Vec);
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+ return DAG.getNode(ISD::VECREDUCE_ADD , DL, VT, Vec);
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}
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// Match (binop (reduce (extract_subvector V, 0),
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// (extract_vector_elt V, sizeof(SubVec))))
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// into a reduction of one more element from the original vector V.
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- if (LHS.getOpcode() != ReduceOpc )
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+ if (LHS.getOpcode() != ISD::VECREDUCE_ADD )
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return SDValue();
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SDValue ReduceVec = LHS.getOperand(0);
@@ -11215,7 +11183,7 @@ combineBinOpOfExtractToReduceTree(SDNode *N, SelectionDAG &DAG,
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EVT ReduceVT = EVT::getVectorVT(*DAG.getContext(), VT, Idx + 1);
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SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec,
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DAG.getVectorIdxConstant(0, DL));
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- return DAG.getNode(ReduceOpc , DL, VT, Vec);
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+ return DAG.getNode(ISD::VECREDUCE_ADD , DL, VT, Vec);
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}
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}
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@@ -11723,8 +11691,6 @@ static SDValue performANDCombine(SDNode *N,
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if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
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return V;
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- if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
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- return V;
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if (DCI.isAfterLegalizeDAG())
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if (SDValue V = combineDeMorganOfBoolean(N, DAG))
@@ -11777,8 +11743,6 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
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if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
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return V;
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- if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
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- return V;
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if (DCI.isAfterLegalizeDAG())
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if (SDValue V = combineDeMorganOfBoolean(N, DAG))
@@ -11830,9 +11794,6 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
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if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
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return V;
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- if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
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- return V;
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-
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// fold (xor (select cond, 0, y), x) ->
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// (select cond, x, (xor x, y))
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return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
@@ -14038,13 +13999,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::SMAX:
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case ISD::SMIN:
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case ISD::FMAXNUM:
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- case ISD::FMINNUM: {
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- if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
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- return V;
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- if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
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- return V;
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- return SDValue();
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- }
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+ case ISD::FMINNUM:
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+ return combineBinOpToReduce(N, DAG, Subtarget);
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case ISD::SETCC:
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return performSETCCCombine(N, DAG, Subtarget);
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case ISD::SIGN_EXTEND_INREG:
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