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Revert "[RISCV] Generaize reduction tree matching to all integer reductions (#68014)"
This reverts commit 7a0b9da and 63bbc25. I'm seeing issues (e.g. on the GCC torture suite) where combineBinOpOfExtractToReduceTree is called when the V extensions aren't enabled and triggers a crash due to RISCVSubtarget::getElen asserting. I'll aim to follow up with a minimal reproducer. Although it's pretty obvious how to avoid this crash with some extra gating, there are a few options as to where that should be inserted so I think it's best to revert and agree the appropriate fix separately.
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-867
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3 files changed

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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+7-51
Original file line numberDiff line numberDiff line change
@@ -11112,31 +11112,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
1111211112
}
1111311113
}
1111411114

11115-
/// Given an integer binary operator, return the generic ISD::VECREDUCE_OP
11116-
/// which corresponds to it.
11117-
static unsigned getVecReduceOpcode(unsigned Opc) {
11118-
switch (Opc) {
11119-
default:
11120-
llvm_unreachable("Unhandled binary to transfrom reduction");
11121-
case ISD::ADD:
11122-
return ISD::VECREDUCE_ADD;
11123-
case ISD::UMAX:
11124-
return ISD::VECREDUCE_UMAX;
11125-
case ISD::SMAX:
11126-
return ISD::VECREDUCE_SMAX;
11127-
case ISD::UMIN:
11128-
return ISD::VECREDUCE_UMIN;
11129-
case ISD::SMIN:
11130-
return ISD::VECREDUCE_SMIN;
11131-
case ISD::AND:
11132-
return ISD::VECREDUCE_AND;
11133-
case ISD::OR:
11134-
return ISD::VECREDUCE_OR;
11135-
case ISD::XOR:
11136-
return ISD::VECREDUCE_XOR;
11137-
}
11138-
}
11139-
1114011115
/// Perform two related transforms whose purpose is to incrementally recognize
1114111116
/// an explode_vector followed by scalar reduction as a vector reduction node.
1114211117
/// This exists to recover from a deficiency in SLP which can't handle
@@ -11155,15 +11130,8 @@ combineBinOpOfExtractToReduceTree(SDNode *N, SelectionDAG &DAG,
1115511130

1115611131
const SDLoc DL(N);
1115711132
const EVT VT = N->getValueType(0);
11158-
11159-
// TODO: Handle floating point here.
11160-
if (!VT.isInteger())
11161-
return SDValue();
11162-
11163-
const unsigned Opc = N->getOpcode();
11164-
const unsigned ReduceOpc = getVecReduceOpcode(Opc);
11165-
assert(Opc == ISD::getVecReduceBaseOpcode(ReduceOpc) &&
11166-
"Inconsistent mappings");
11133+
[[maybe_unused]] const unsigned Opc = N->getOpcode();
11134+
assert(Opc == ISD::ADD && "extend this to other reduction types");
1116711135
const SDValue LHS = N->getOperand(0);
1116811136
const SDValue RHS = N->getOperand(1);
1116911137

@@ -11193,13 +11161,13 @@ combineBinOpOfExtractToReduceTree(SDNode *N, SelectionDAG &DAG,
1119311161
EVT ReduceVT = EVT::getVectorVT(*DAG.getContext(), VT, 2);
1119411162
SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec,
1119511163
DAG.getVectorIdxConstant(0, DL));
11196-
return DAG.getNode(ReduceOpc, DL, VT, Vec);
11164+
return DAG.getNode(ISD::VECREDUCE_ADD, DL, VT, Vec);
1119711165
}
1119811166

1119911167
// Match (binop (reduce (extract_subvector V, 0),
1120011168
// (extract_vector_elt V, sizeof(SubVec))))
1120111169
// into a reduction of one more element from the original vector V.
11202-
if (LHS.getOpcode() != ReduceOpc)
11170+
if (LHS.getOpcode() != ISD::VECREDUCE_ADD)
1120311171
return SDValue();
1120411172

1120511173
SDValue ReduceVec = LHS.getOperand(0);
@@ -11215,7 +11183,7 @@ combineBinOpOfExtractToReduceTree(SDNode *N, SelectionDAG &DAG,
1121511183
EVT ReduceVT = EVT::getVectorVT(*DAG.getContext(), VT, Idx + 1);
1121611184
SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec,
1121711185
DAG.getVectorIdxConstant(0, DL));
11218-
return DAG.getNode(ReduceOpc, DL, VT, Vec);
11186+
return DAG.getNode(ISD::VECREDUCE_ADD, DL, VT, Vec);
1121911187
}
1122011188
}
1122111189

@@ -11723,8 +11691,6 @@ static SDValue performANDCombine(SDNode *N,
1172311691

1172411692
if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
1172511693
return V;
11726-
if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
11727-
return V;
1172811694

1172911695
if (DCI.isAfterLegalizeDAG())
1173011696
if (SDValue V = combineDeMorganOfBoolean(N, DAG))
@@ -11777,8 +11743,6 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1177711743

1177811744
if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
1177911745
return V;
11780-
if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
11781-
return V;
1178211746

1178311747
if (DCI.isAfterLegalizeDAG())
1178411748
if (SDValue V = combineDeMorganOfBoolean(N, DAG))
@@ -11830,9 +11794,6 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
1183011794

1183111795
if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
1183211796
return V;
11833-
if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
11834-
return V;
11835-
1183611797
// fold (xor (select cond, 0, y), x) ->
1183711798
// (select cond, x, (xor x, y))
1183811799
return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
@@ -14038,13 +13999,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1403813999
case ISD::SMAX:
1403914000
case ISD::SMIN:
1404014001
case ISD::FMAXNUM:
14041-
case ISD::FMINNUM: {
14042-
if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
14043-
return V;
14044-
if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
14045-
return V;
14046-
return SDValue();
14047-
}
14002+
case ISD::FMINNUM:
14003+
return combineBinOpToReduce(N, DAG, Subtarget);
1404814004
case ISD::SETCC:
1404914005
return performSETCCCombine(N, DAG, Subtarget);
1405014006
case ISD::SIGN_EXTEND_INREG:

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