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cast to unsigned
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llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2811,14 +2811,16 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
28112811
unsigned selectOp;
28122812
unsigned addOp;
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if (isScalarRes) {
2814-
NegOneReg = GR.getOrCreateConstInt(-1, I, ResType, TII, ZeroAsNull);
2814+
NegOneReg =
2815+
GR.getOrCreateConstInt((unsigned)-1, I, ResType, TII, ZeroAsNull);
28152816
Reg0 = GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull);
28162817
Reg32 = GR.getOrCreateConstInt(32, I, ResType, TII, ZeroAsNull);
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selectOp = SPIRV::OpSelectSISCond;
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addOp = SPIRV::OpIAddS;
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} else {
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BoolType = GR.getOrCreateSPIRVVectorType(BoolType, count, MIRBuilder);
2821-
NegOneReg = GR.getOrCreateConstVector(-1, I, ResType, TII, ZeroAsNull);
2822+
NegOneReg =
2823+
GR.getOrCreateConstVector((unsigned)-1, I, ResType, TII, ZeroAsNull);
28222824
Reg0 = GR.getOrCreateConstVector(0, I, ResType, TII, ZeroAsNull);
28232825
Reg32 = GR.getOrCreateConstVector(32, I, ResType, TII, ZeroAsNull);
28242826
selectOp = SPIRV::OpSelectVIVCond;

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