@@ -2811,14 +2811,16 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
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unsigned selectOp;
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unsigned addOp;
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if (isScalarRes) {
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- NegOneReg = GR.getOrCreateConstInt (-1 , I, ResType , TII, ZeroAsNull);
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+ NegOneReg =
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+ GR.getOrCreateConstInt ((unsigned )-1 , I, ResType , TII, ZeroAsNull);
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Reg0 = GR.getOrCreateConstInt (0 , I, ResType , TII, ZeroAsNull);
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Reg32 = GR.getOrCreateConstInt (32 , I, ResType , TII, ZeroAsNull);
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selectOp = SPIRV::OpSelectSISCond;
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addOp = SPIRV::OpIAddS;
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} else {
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BoolType = GR.getOrCreateSPIRVVectorType (BoolType, count, MIRBuilder);
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- NegOneReg = GR.getOrCreateConstVector (-1 , I, ResType , TII, ZeroAsNull);
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+ NegOneReg =
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+ GR.getOrCreateConstVector ((unsigned )-1 , I, ResType , TII, ZeroAsNull);
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Reg0 = GR.getOrCreateConstVector (0 , I, ResType , TII, ZeroAsNull);
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Reg32 = GR.getOrCreateConstVector (32 , I, ResType , TII, ZeroAsNull);
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selectOp = SPIRV::OpSelectVIVCond;
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