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jayfoadjayfoad
authoredFeb 16, 2024
[AMDGPU] Set DecoderNamespace consistently for GFX10+ MIMG instructions (#81881)
This was done inconsistently before. Many instructions used the default "AMDGPU" namespace which I would like to remove.
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‎llvm/lib/Target/AMDGPU/MIMGInstructions.td

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -527,16 +527,16 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
527527
let ssamp = 0 in {
528528
if op.HAS_GFX10M then {
529529
def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
530-
!if(enableDisasm, "AMDGPU", "")>;
530+
!if(enableDisasm, "GFX10", "")>;
531531
if !not(ExtendedImageInst) then
532532
def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32,
533533
!if(enableDisasm, "GFX90A", "")>;
534534
def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32,
535-
!if(enableDisasm, "AMDGPU", "")>;
535+
!if(enableDisasm, "GFX10", "")>;
536536
}
537537
if op.HAS_GFX11 then {
538538
def _V1_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPR_32,
539-
!if(enableDisasm, "AMDGPU", "")>;
539+
!if(enableDisasm, "GFX11", "")>;
540540
}
541541
}
542542
if op.HAS_GFX12 then {
@@ -606,12 +606,12 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
606606
def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128>;
607607
def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>;
608608
def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4,
609-
!if(enableDisasm, "AMDGPU", "")>;
609+
!if(enableDisasm, "GFX10", "")>;
610610
}
611611
if op.HAS_GFX11 then {
612612
def _V4_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_128>;
613613
def _V4_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 4,
614-
!if(enableDisasm, "AMDGPU", "")>;
614+
!if(enableDisasm, "GFX11", "")>;
615615
}
616616
}
617617
if op.HAS_GFX12 then {
@@ -754,16 +754,16 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
754754
let ssamp = 0 in {
755755
if op.HAS_GFX10M then {
756756
def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32,
757-
!if(enableDisasm, "AMDGPU", "")>;
757+
!if(enableDisasm, "GFX10", "")>;
758758
let hasPostISelHook = 1 in
759759
def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32,
760760
!if(enableDisasm, "GFX90A", "")>;
761761
def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32,
762-
!if(enableDisasm, "AMDGPU", "")>;
762+
!if(enableDisasm, "GFX10", "")>;
763763
}
764764
if op.HAS_GFX11 then {
765765
def _V1_gfx11 : MIMG_Store_gfx11 <op, asm, data_rc, VGPR_32,
766-
!if(enableDisasm, "AMDGPU", "")>;
766+
!if(enableDisasm, "GFX11", "")>;
767767
}
768768
}
769769
if op.HAS_GFX12 then {
@@ -812,12 +812,12 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
812812
def _V4_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_128>;
813813
def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>;
814814
def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4,
815-
!if(enableDisasm, "AMDGPU", "")>;
815+
!if(enableDisasm, "GFX10", "")>;
816816
}
817817
if op.HAS_GFX11 then {
818818
def _V4_gfx11 : MIMG_Store_gfx11 <op, asm, data_rc, VReg_128>;
819819
def _V4_nsa_gfx11 : MIMG_Store_nsa_gfx11 <op, asm, data_rc, 4,
820-
!if(enableDisasm, "AMDGPU", "")>;
820+
!if(enableDisasm, "GFX11", "")>;
821821
}
822822
}
823823
if op.HAS_GFX12 then {
@@ -897,7 +897,7 @@ class MIMG_Atomic_gfx10<mimgopc op, string opcode,
897897
RegisterClass DataRC, RegisterClass AddrRC,
898898
bit enableDisasm = 0>
899899
: MIMG_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst),
900-
!if(enableDisasm, "AMDGPU", "")> {
900+
!if(enableDisasm, "GFX10", "")> {
901901
let Constraints = "$vdst = $vdata";
902902

903903
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
@@ -910,7 +910,7 @@ class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode,
910910
RegisterClass DataRC, int num_addrs,
911911
bit enableDisasm = 0>
912912
: MIMG_nsa_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst), num_addrs,
913-
!if(enableDisasm, "AMDGPU", "")> {
913+
!if(enableDisasm, "GFX10", "")> {
914914
let Constraints = "$vdst = $vdata";
915915

916916
let InOperandList = !con((ins DataRC:$vdata),
@@ -925,7 +925,7 @@ class MIMG_Atomic_gfx11<mimgopc op, string opcode,
925925
RegisterClass DataRC, RegisterClass AddrRC,
926926
bit enableDisasm = 0>
927927
: MIMG_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst),
928-
!if(enableDisasm, "AMDGPU", "")> {
928+
!if(enableDisasm, "GFX11", "")> {
929929
let Constraints = "$vdst = $vdata";
930930

931931
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
@@ -938,7 +938,7 @@ class MIMG_Atomic_nsa_gfx11<mimgopc op, string opcode,
938938
RegisterClass DataRC, int num_addrs,
939939
bit enableDisasm = 0>
940940
: MIMG_nsa_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst), num_addrs,
941-
!if(enableDisasm, "AMDGPU", "")> {
941+
!if(enableDisasm, "GFX11", "")> {
942942
let Constraints = "$vdst = $vdata";
943943

944944
let InOperandList = !con((ins DataRC:$vdata),
@@ -1298,19 +1298,19 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
12981298
if op.HAS_GFX10M then {
12991299
def _V # addr.NumWords
13001300
: MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass,
1301-
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
1301+
!if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
13021302
if !not(ExtendedImageInst) then
13031303
def _V # addr.NumWords # _gfx90a
13041304
: MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass,
13051305
!if(!and(enableDisasm, addr.Disassemble), "GFX90A", "")>;
13061306
def _V # addr.NumWords # _gfx10
13071307
: MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass,
1308-
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
1308+
!if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
13091309
}
13101310
if op.HAS_GFX11 then {
13111311
def _V # addr.NumWords # _gfx11
13121312
: MIMG_Sampler_gfx11 <op, asm, dst_rc, addr.RegClass,
1313-
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
1313+
!if(!and(enableDisasm, addr.Disassemble), "GFX11", "")>;
13141314
}
13151315
}
13161316
}
@@ -1320,7 +1320,7 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
13201320
if op.HAS_GFX10M then {
13211321
def _V # addr.NumWords # _nsa_gfx10
13221322
: MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords,
1323-
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
1323+
!if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
13241324
}
13251325
}
13261326
}
@@ -1330,7 +1330,7 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
13301330
if op.HAS_GFX11 then {
13311331
def _V # addr.NumWords # _nsa_gfx11
13321332
: MIMG_Sampler_nsa_gfx11<op, asm, dst_rc, addr.NumWords, addr.RegClass,
1333-
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
1333+
!if(!and(enableDisasm, addr.Disassemble), "GFX11", "")>;
13341334
}
13351335
}
13361336
}
@@ -1416,21 +1416,21 @@ class MIMG_IntersectRay_Helper<bit Is64, bit IsA16> {
14161416
}
14171417

14181418
class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC>
1419-
: MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "AMDGPU"> {
1419+
: MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "GFX10"> {
14201420
let InOperandList = (ins AddrRC:$vaddr0, SReg_128:$srsrc, A16:$a16);
14211421
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";
14221422

14231423
let nsa = 0;
14241424
}
14251425

14261426
class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs>
1427-
: MIMG_nsa_gfx10<op.GFX10M, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> {
1427+
: MIMG_nsa_gfx10<op.GFX10M, (outs VReg_128:$vdata), num_addrs, "GFX10"> {
14281428
let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$srsrc, A16:$a16));
14291429
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";
14301430
}
14311431

14321432
class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterClass AddrRC>
1433-
: MIMG_gfx11<op.GFX11, (outs VReg_128:$vdata), "AMDGPU"> {
1433+
: MIMG_gfx11<op.GFX11, (outs VReg_128:$vdata), "GFX11"> {
14341434
let InOperandList = (ins AddrRC:$vaddr0, SReg_128:$srsrc, A16:$a16);
14351435
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";
14361436

@@ -1439,7 +1439,7 @@ class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterClass AddrRC>
14391439

14401440
class MIMG_IntersectRay_nsa_gfx11<mimgopc op, string opcode, int num_addrs,
14411441
list<RegisterClass> addr_types>
1442-
: MIMG_nsa_gfx11<op.GFX11, (outs VReg_128:$vdata), num_addrs, "AMDGPU",
1442+
: MIMG_nsa_gfx11<op.GFX11, (outs VReg_128:$vdata), num_addrs, "GFX11",
14431443
addr_types> {
14441444
let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$srsrc, A16:$a16));
14451445
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";

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