Skip to content

Commit 957e1bc

Browse files
committed
[LoopDist] Add some runtime checks for cross partition loads
Emit safety guards for ptr accesses when cross partition loads exist which have a corresponding store to the same address in a different partition. This will emit the necessary ptr checks for these accesses.
1 parent 96bbe47 commit 957e1bc

File tree

2 files changed

+223
-0
lines changed

2 files changed

+223
-0
lines changed

llvm/lib/Transforms/Scalar/LoopDistribute.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -521,6 +521,22 @@ class InstPartitionContainer {
521521
Partition = -1;
522522
}
523523
assert(Partition != -2 && "Pointer not belonging to any partition");
524+
// All the store context uses of our address were processed,
525+
// Now make sure we don't have cross partition loads.
526+
if (RtPtrCheck->Pointers[I].IsWritePtr) {
527+
if (Ptr->hasOneUse() || Partition == -1)
528+
continue;
529+
530+
for (User *U : Ptr->users())
531+
if (auto *CurLoad = dyn_cast<LoadInst>(U))
532+
if (L->contains(CurLoad->getParent()))
533+
if (Partition != (int)this->InstToPartitionId[CurLoad]) {
534+
// -1 means belonging to multiple partitions.
535+
Partition = -1;
536+
break;
537+
}
538+
539+
}
524540
}
525541

526542
return PtrToPartitions;
Lines changed: 207 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,207 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -aa-pipeline=basic-aa -passes=loop-simplify,loop-distribute -enable-loop-distribute -verify-loop-info -verify-dom-info -S %s | FileCheck %s
3+
4+
; Test emit safety guards for ptr access of %a and %c on a cross parition load which
5+
; has a corresponding store to the same address. This ensures that if %a and %c
6+
; overlap in some scenarios, that we execute the original loop for safety reasons.
7+
8+
define dso_local void @_Z13distribution3PiS_S_S_i(ptr nocapture noundef %a, ptr nocapture noundef readonly %b, ptr nocapture noundef %c, ptr nocapture noundef writeonly %d, i32 noundef signext %len) {
9+
; CHECK-LABEL: define dso_local void @_Z13distribution3PiS_S_S_i(
10+
; CHECK-SAME: ptr noundef captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]], ptr noundef captures(none) [[C:%.*]], ptr noundef writeonly captures(none) [[D:%.*]], i32 noundef signext [[LEN:%.*]]) {
11+
; CHECK-NEXT: [[ENTRY:.*:]]
12+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[LEN]], 0
13+
; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
14+
; CHECK: [[IF_THEN]]:
15+
; CHECK-NEXT: [[SUB_NEG:%.*]] = add nsw i32 [[LEN]], -2147483647
16+
; CHECK-NEXT: [[CMP1_NOT51:%.*]] = icmp eq i32 [[LEN]], 1
17+
; CHECK-NEXT: br i1 [[CMP1_NOT51]], label %[[IF_END]], label %[[FOR_BODY_PREHEADER:.*]]
18+
; CHECK: [[FOR_BODY_PREHEADER]]:
19+
; CHECK-NEXT: [[ADD:%.*]] = sub nuw i32 -2147483648, [[LEN]]
20+
; CHECK-NEXT: [[I:%.*]] = zext nneg i32 [[ADD]] to i64
21+
; CHECK-NEXT: br label %[[FOR_BODY_LVER_CHECK:.*]]
22+
; CHECK: [[FOR_BODY_LVER_CHECK]]:
23+
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 4
24+
; CHECK-NEXT: [[TMP0:%.*]] = sub i32 -2147483647, [[LEN]]
25+
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
26+
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i64 [[TMP1]], 2
27+
; CHECK-NEXT: [[TMP3:%.*]] = sub i64 8589934596, [[TMP2]]
28+
; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP3]]
29+
; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[C]], i64 [[TMP3]]
30+
; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[D]], i64 4
31+
; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[D]], i64 [[TMP3]]
32+
; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[B]], i64 4
33+
; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP3]]
34+
; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP2]]
35+
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[C]], [[SCEVGEP1]]
36+
; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
37+
; CHECK-NEXT: [[BOUND07:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP4]]
38+
; CHECK-NEXT: [[BOUND18:%.*]] = icmp ult ptr [[SCEVGEP3]], [[SCEVGEP1]]
39+
; CHECK-NEXT: [[FOUND_CONFLICT9:%.*]] = and i1 [[BOUND07]], [[BOUND18]]
40+
; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT9]]
41+
; CHECK-NEXT: [[BOUND010:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP6]]
42+
; CHECK-NEXT: [[BOUND111:%.*]] = icmp ult ptr [[SCEVGEP5]], [[SCEVGEP1]]
43+
; CHECK-NEXT: [[FOUND_CONFLICT12:%.*]] = and i1 [[BOUND010]], [[BOUND111]]
44+
; CHECK-NEXT: [[CONFLICT_RDX13:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT12]]
45+
; CHECK-NEXT: [[BOUND014:%.*]] = icmp ult ptr [[C]], [[SCEVGEP4]]
46+
; CHECK-NEXT: [[BOUND115:%.*]] = icmp ult ptr [[SCEVGEP3]], [[SCEVGEP2]]
47+
; CHECK-NEXT: [[FOUND_CONFLICT16:%.*]] = and i1 [[BOUND014]], [[BOUND115]]
48+
; CHECK-NEXT: [[CONFLICT_RDX17:%.*]] = or i1 [[CONFLICT_RDX13]], [[FOUND_CONFLICT16]]
49+
; CHECK-NEXT: [[BOUND018:%.*]] = icmp ult ptr [[SCEVGEP3]], [[SCEVGEP6]]
50+
; CHECK-NEXT: [[BOUND119:%.*]] = icmp ult ptr [[SCEVGEP5]], [[SCEVGEP4]]
51+
; CHECK-NEXT: [[FOUND_CONFLICT20:%.*]] = and i1 [[BOUND018]], [[BOUND119]]
52+
; CHECK-NEXT: [[CONFLICT_RDX21:%.*]] = or i1 [[CONFLICT_RDX17]], [[FOUND_CONFLICT20]]
53+
; CHECK-NEXT: [[TMP4:%.*]] = sub i32 -2147483647, [[LEN]]
54+
; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
55+
; CHECK-NEXT: [[TMP6:%.*]] = sub i64 2147483647, [[TMP5]]
56+
; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
57+
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP4]], [[TMP7]]
58+
; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], [[TMP4]]
59+
; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP6]], 4294967295
60+
; CHECK-NEXT: [[TMP11:%.*]] = or i1 [[TMP9]], [[TMP10]]
61+
; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP6]] to i32
62+
; CHECK-NEXT: [[TMP13:%.*]] = add i32 1, [[TMP12]]
63+
; CHECK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[TMP13]], 1
64+
; CHECK-NEXT: [[TMP15:%.*]] = icmp ugt i64 [[TMP6]], 4294967295
65+
; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP14]], [[TMP15]]
66+
; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP11]], [[TMP16]]
67+
; CHECK-NEXT: [[LVER_SAFE:%.*]] = or i1 [[CONFLICT_RDX21]], [[TMP17]]
68+
; CHECK-NEXT: br i1 [[LVER_SAFE]], label %[[FOR_BODY_PH_LVER_ORIG:.*]], label %[[FOR_BODY_PH_LDIST1:.*]]
69+
; CHECK: [[FOR_BODY_PH_LVER_ORIG]]:
70+
; CHECK-NEXT: br label %[[FOR_BODY_LVER_ORIG:.*]]
71+
; CHECK: [[FOR_BODY_LVER_ORIG]]:
72+
; CHECK-NEXT: [[INDVARS_IV_LVER_ORIG:%.*]] = phi i64 [ [[I]], %[[FOR_BODY_PH_LVER_ORIG]] ], [ [[INDVARS_IV_NEXT_LVER_ORIG:%.*]], %[[FOR_BODY_LVER_ORIG]] ]
73+
; CHECK-NEXT: [[I1_LVER_ORIG:%.*]] = trunc i64 [[INDVARS_IV_LVER_ORIG]] to i32
74+
; CHECK-NEXT: [[SUB3_LVER_ORIG:%.*]] = add i32 [[SUB_NEG]], [[I1_LVER_ORIG]]
75+
; CHECK-NEXT: [[IDXPROM_LVER_ORIG:%.*]] = sext i32 [[SUB3_LVER_ORIG]] to i64
76+
; CHECK-NEXT: [[ARRAYIDX_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IDXPROM_LVER_ORIG]]
77+
; CHECK-NEXT: [[I2_LVER_ORIG:%.*]] = load i32, ptr [[ARRAYIDX_LVER_ORIG]], align 4, !tbaa [[TBAA0:![0-9]+]]
78+
; CHECK-NEXT: [[ADD4_LVER_ORIG:%.*]] = add nsw i32 [[I2_LVER_ORIG]], 1
79+
; CHECK-NEXT: [[ARRAYIDX8_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDXPROM_LVER_ORIG]]
80+
; CHECK-NEXT: store i32 [[ADD4_LVER_ORIG]], ptr [[ARRAYIDX8_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
81+
; CHECK-NEXT: [[I3_LVER_ORIG:%.*]] = getelementptr i32, ptr [[C]], i64 [[IDXPROM_LVER_ORIG]]
82+
; CHECK-NEXT: [[ARRAYIDX17_LVER_ORIG:%.*]] = getelementptr i8, ptr [[I3_LVER_ORIG]], i64 -4
83+
; CHECK-NEXT: [[I4_LVER_ORIG:%.*]] = load i32, ptr [[ARRAYIDX17_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
84+
; CHECK-NEXT: [[SUB18_LVER_ORIG:%.*]] = sub nsw i32 [[ADD4_LVER_ORIG]], [[I4_LVER_ORIG]]
85+
; CHECK-NEXT: store i32 [[SUB18_LVER_ORIG]], ptr [[I3_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
86+
; CHECK-NEXT: [[I5_LVER_ORIG:%.*]] = load i32, ptr [[ARRAYIDX8_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
87+
; CHECK-NEXT: [[ADD27_LVER_ORIG:%.*]] = add nsw i32 [[I5_LVER_ORIG]], 2
88+
; CHECK-NEXT: [[ARRAYIDX31_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[D]], i64 [[IDXPROM_LVER_ORIG]]
89+
; CHECK-NEXT: store i32 [[ADD27_LVER_ORIG]], ptr [[ARRAYIDX31_LVER_ORIG]], align 4, !tbaa [[TBAA0]]
90+
; CHECK-NEXT: [[INDVARS_IV_NEXT_LVER_ORIG]] = add i64 [[INDVARS_IV_LVER_ORIG]], 1
91+
; CHECK-NEXT: [[I6_LVER_ORIG:%.*]] = and i64 [[INDVARS_IV_NEXT_LVER_ORIG]], 4294967295
92+
; CHECK-NEXT: [[CMP1_NOT_LVER_ORIG:%.*]] = icmp eq i64 [[I6_LVER_ORIG]], 2147483647
93+
; CHECK-NEXT: br i1 [[CMP1_NOT_LVER_ORIG]], label %[[IF_END_LOOPEXIT_LOOPEXIT:.*]], label %[[FOR_BODY_LVER_ORIG]], !llvm.loop [[LOOP4:![0-9]+]]
94+
; CHECK: [[FOR_BODY_PH_LDIST1]]:
95+
; CHECK-NEXT: br label %[[FOR_BODY_LDIST1:.*]]
96+
; CHECK: [[FOR_BODY_LDIST1]]:
97+
; CHECK-NEXT: [[INDVARS_IV_LDIST1:%.*]] = phi i64 [ [[I]], %[[FOR_BODY_PH_LDIST1]] ], [ [[INDVARS_IV_NEXT_LDIST1:%.*]], %[[FOR_BODY_LDIST1]] ]
98+
; CHECK-NEXT: [[I1_LDIST1:%.*]] = trunc i64 [[INDVARS_IV_LDIST1]] to i32
99+
; CHECK-NEXT: [[SUB3_LDIST1:%.*]] = add i32 [[SUB_NEG]], [[I1_LDIST1]]
100+
; CHECK-NEXT: [[IDXPROM_LDIST1:%.*]] = sext i32 [[SUB3_LDIST1]] to i64
101+
; CHECK-NEXT: [[ARRAYIDX_LDIST1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IDXPROM_LDIST1]]
102+
; CHECK-NEXT: [[I2_LDIST1:%.*]] = load i32, ptr [[ARRAYIDX_LDIST1]], align 4, !tbaa [[TBAA0]], !alias.scope [[META6:![0-9]+]]
103+
; CHECK-NEXT: [[ADD4_LDIST1:%.*]] = add nsw i32 [[I2_LDIST1]], 1
104+
; CHECK-NEXT: [[ARRAYIDX8_LDIST1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDXPROM_LDIST1]]
105+
; CHECK-NEXT: store i32 [[ADD4_LDIST1]], ptr [[ARRAYIDX8_LDIST1]], align 4, !tbaa [[TBAA0]], !alias.scope [[META9:![0-9]+]], !noalias [[META11:![0-9]+]]
106+
; CHECK-NEXT: [[I3_LDIST1:%.*]] = getelementptr i32, ptr [[C]], i64 [[IDXPROM_LDIST1]]
107+
; CHECK-NEXT: [[ARRAYIDX17_LDIST1:%.*]] = getelementptr i8, ptr [[I3_LDIST1]], i64 -4
108+
; CHECK-NEXT: [[I4_LDIST1:%.*]] = load i32, ptr [[ARRAYIDX17_LDIST1]], align 4, !tbaa [[TBAA0]], !alias.scope [[META14:![0-9]+]], !noalias [[META15:![0-9]+]]
109+
; CHECK-NEXT: [[SUB18_LDIST1:%.*]] = sub nsw i32 [[ADD4_LDIST1]], [[I4_LDIST1]]
110+
; CHECK-NEXT: store i32 [[SUB18_LDIST1]], ptr [[I3_LDIST1]], align 4, !tbaa [[TBAA0]], !alias.scope [[META14]], !noalias [[META15]]
111+
; CHECK-NEXT: [[INDVARS_IV_NEXT_LDIST1]] = add i64 [[INDVARS_IV_LDIST1]], 1
112+
; CHECK-NEXT: [[I6_LDIST1:%.*]] = and i64 [[INDVARS_IV_NEXT_LDIST1]], 4294967295
113+
; CHECK-NEXT: [[CMP1_NOT_LDIST1:%.*]] = icmp eq i64 [[I6_LDIST1]], 2147483647
114+
; CHECK-NEXT: br i1 [[CMP1_NOT_LDIST1]], label %[[FOR_BODY_PH:.*]], label %[[FOR_BODY_LDIST1]], !llvm.loop [[LOOP16:![0-9]+]]
115+
; CHECK: [[FOR_BODY_PH]]:
116+
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
117+
; CHECK: [[FOR_BODY]]:
118+
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[I]], %[[FOR_BODY_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
119+
; CHECK-NEXT: [[I1:%.*]] = trunc i64 [[INDVARS_IV]] to i32
120+
; CHECK-NEXT: [[SUB3:%.*]] = add i32 [[SUB_NEG]], [[I1]]
121+
; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB3]] to i64
122+
; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDXPROM]]
123+
; CHECK-NEXT: [[I5:%.*]] = load i32, ptr [[ARRAYIDX8]], align 4, !tbaa [[TBAA0]], !alias.scope [[META9]], !noalias [[META11]]
124+
; CHECK-NEXT: [[ADD27:%.*]] = add nsw i32 [[I5]], 2
125+
; CHECK-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds i32, ptr [[D]], i64 [[IDXPROM]]
126+
; CHECK-NEXT: store i32 [[ADD27]], ptr [[ARRAYIDX31]], align 4, !tbaa [[TBAA0]], !alias.scope [[META15]], !noalias [[META6]]
127+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
128+
; CHECK-NEXT: [[I6:%.*]] = and i64 [[INDVARS_IV_NEXT]], 4294967295
129+
; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[I6]], 2147483647
130+
; CHECK-NEXT: br i1 [[CMP1_NOT]], label %[[IF_END_LOOPEXIT_LOOPEXIT22:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP16]]
131+
; CHECK: [[IF_END_LOOPEXIT_LOOPEXIT]]:
132+
; CHECK-NEXT: br label %[[IF_END_LOOPEXIT:.*]]
133+
; CHECK: [[IF_END_LOOPEXIT_LOOPEXIT22]]:
134+
; CHECK-NEXT: br label %[[IF_END_LOOPEXIT]]
135+
; CHECK: [[IF_END_LOOPEXIT]]:
136+
; CHECK-NEXT: br label %[[IF_END]]
137+
; CHECK: [[IF_END]]:
138+
; CHECK-NEXT: ret void
139+
;
140+
entry:
141+
%cmp = icmp sgt i32 %len, 0
142+
br i1 %cmp, label %if.then, label %if.end
143+
144+
if.then: ; preds = %entry
145+
%sub.neg = add nsw i32 %len, -2147483647
146+
%cmp1.not51 = icmp eq i32 %len, 1
147+
br i1 %cmp1.not51, label %if.end, label %for.body.preheader
148+
149+
for.body.preheader: ; preds = %if.then
150+
%add = sub nuw i32 -2147483648, %len
151+
%i = zext nneg i32 %add to i64
152+
br label %for.body
153+
154+
for.body: ; preds = %for.body, %for.body.preheader
155+
%indvars.iv = phi i64 [ %i, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
156+
%i1 = trunc i64 %indvars.iv to i32
157+
%sub3 = add i32 %sub.neg, %i1
158+
%idxprom = sext i32 %sub3 to i64
159+
%arrayidx = getelementptr inbounds i32, ptr %b, i64 %idxprom
160+
%i2 = load i32, ptr %arrayidx, align 4, !tbaa !9
161+
%add4 = add nsw i32 %i2, 1
162+
%arrayidx8 = getelementptr inbounds i32, ptr %a, i64 %idxprom
163+
store i32 %add4, ptr %arrayidx8, align 4, !tbaa !9
164+
%i3 = getelementptr i32, ptr %c, i64 %idxprom
165+
%arrayidx17 = getelementptr i8, ptr %i3, i64 -4
166+
%i4 = load i32, ptr %arrayidx17, align 4, !tbaa !9
167+
%sub18 = sub nsw i32 %add4, %i4
168+
store i32 %sub18, ptr %i3, align 4, !tbaa !9
169+
%i5 = load i32, ptr %arrayidx8, align 4, !tbaa !9
170+
%add27 = add nsw i32 %i5, 2
171+
%arrayidx31 = getelementptr inbounds i32, ptr %d, i64 %idxprom
172+
store i32 %add27, ptr %arrayidx31, align 4, !tbaa !9
173+
%indvars.iv.next = add i64 %indvars.iv, 1
174+
%i6 = and i64 %indvars.iv.next, 4294967295
175+
%cmp1.not = icmp eq i64 %i6, 2147483647
176+
br i1 %cmp1.not, label %if.end, label %for.body, !llvm.loop !13
177+
178+
if.end: ; preds = %for.body, %if.then, %entry
179+
ret void
180+
}
181+
182+
!0 = !{i32 1, !"wchar_size", i32 4}
183+
!9 = !{!10, !10, i64 0}
184+
!10 = !{!"int", !11, i64 0}
185+
!11 = !{!"omnipotent char", !12, i64 0}
186+
!12 = !{!"Simple C++ TBAA"}
187+
!13 = distinct !{!13, !14}
188+
!14 = !{!"llvm.loop.mustprogress"}
189+
;.
190+
; CHECK: [[TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
191+
; CHECK: [[META1]] = !{!"int", [[META2:![0-9]+]], i64 0}
192+
; CHECK: [[META2]] = !{!"omnipotent char", [[META3:![0-9]+]], i64 0}
193+
; CHECK: [[META3]] = !{!"Simple C++ TBAA"}
194+
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]}
195+
; CHECK: [[META5]] = !{!"llvm.loop.mustprogress"}
196+
; CHECK: [[META6]] = !{[[META7:![0-9]+]]}
197+
; CHECK: [[META7]] = distinct !{[[META7]], [[META8:![0-9]+]]}
198+
; CHECK: [[META8]] = distinct !{[[META8]], !"LVerDomain"}
199+
; CHECK: [[META9]] = !{[[META10:![0-9]+]]}
200+
; CHECK: [[META10]] = distinct !{[[META10]], [[META8]]}
201+
; CHECK: [[META11]] = !{[[META12:![0-9]+]], [[META13:![0-9]+]], [[META7]]}
202+
; CHECK: [[META12]] = distinct !{[[META12]], [[META8]]}
203+
; CHECK: [[META13]] = distinct !{[[META13]], [[META8]]}
204+
; CHECK: [[META14]] = !{[[META12]]}
205+
; CHECK: [[META15]] = !{[[META13]]}
206+
; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META5]]}
207+
;.

0 commit comments

Comments
 (0)