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[AMDGPU][AsmParser][NFC] Refine parsing of NamedOperandU32 operands.
Eliminates the need for the custom code in parseCustomOperand(). Part of <#62629>. Reviewed By: dp Differential Revision: https://reviews.llvm.org/D150980
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+28
-68
lines changed

3 files changed

+28
-68
lines changed

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 2 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1761,7 +1761,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17611761
AMDGPUOperand::Ptr defaultSMEMOffsetMod() const;
17621762
AMDGPUOperand::Ptr defaultFlatOffset() const;
17631763

1764-
OperandMatchResultTy parseOModOperand(OperandVector &Operands);
1764+
OperandMatchResultTy parseOModSI(OperandVector &Operands);
17651765

17661766
void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
17671767
OptionalImmIndexMap &OptionalIdx);
@@ -8048,7 +8048,7 @@ void AMDGPUAsmParser::onBeginOfFile() {
80488048
getTargetStreamer().EmitDirectiveAMDGCNTarget();
80498049
}
80508050

8051-
OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) {
8051+
OperandMatchResultTy AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {
80528052
StringRef Name = getTokenStr();
80538053
if (Name == "mul") {
80548054
return parseIntWithPrefix("mul", Operands,
@@ -9129,24 +9129,8 @@ AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) {
91299129
return parseTokenOp("off", Operands);
91309130
case MCK_row_95_en:
91319131
return parseTokenOp("row_en", Operands);
9132-
case MCK_ImmCPol:
9133-
return parseCPol(Operands);
91349132
case MCK_gds:
91359133
return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);
9136-
case MCK_ImmNegHi:
9137-
return parseOperandArrayWithPrefix("neg_hi", Operands,
9138-
AMDGPUOperand::ImmTyNegHi);
9139-
case MCK_ImmNegLo:
9140-
return parseOperandArrayWithPrefix("neg_lo", Operands,
9141-
AMDGPUOperand::ImmTyNegLo);
9142-
case MCK_ImmOModSI:
9143-
return parseOModOperand(Operands);
9144-
case MCK_ImmOpSel:
9145-
return parseOperandArrayWithPrefix("op_sel", Operands,
9146-
AMDGPUOperand::ImmTyOpSel);
9147-
case MCK_ImmOpSelHi:
9148-
return parseOperandArrayWithPrefix("op_sel_hi", Operands,
9149-
AMDGPUOperand::ImmTyOpSelHi);
91509134
case MCK_tfe:
91519135
return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);
91529136
}

llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 25 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1121,15 +1121,6 @@ def SDWAVopcDst : BoolRC {
11211121
let PrintMethod = "printVOPDst";
11221122
}
11231123

1124-
class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
1125-
let Name = "Imm"#CName;
1126-
let PredicateMethod = "is"#CName;
1127-
let ParserMethod = !if(Optional, "", "parse"#CName);
1128-
let RenderMethod = "addImmOperands";
1129-
let IsOptional = Optional;
1130-
let DefaultMethod = !if(Optional, "default"#CName, ?);
1131-
}
1132-
11331124
class CustomOperandClass<string CName, bit Optional> : AsmOperandClass {
11341125
let Name = CName;
11351126
let PredicateMethod = "is"#CName;
@@ -1143,6 +1134,7 @@ class CustomOperandProps<bit Optional = 0, string Name = NAME,
11431134
AsmOperandClass Class = CustomOperandClass<Name, Optional>> {
11441135
string PrintMethod = "print"#Name;
11451136
AsmOperandClass ParserMatchClass = Class;
1137+
string OperandType = "OPERAND_IMMEDIATE";
11461138
}
11471139

11481140
class CustomOperand<ValueType Type, bit Optional = 0, string Name = NAME,
@@ -1173,33 +1165,10 @@ class BitOperandClass<string Id, string Name>
11731165
class NamedBitOperand<string Id, string Name = NAME>
11741166
: CustomOperand<i1, 1, Name, BitOperandClass<Id, Name>>;
11751167

1176-
class DefaultOperand_0<CustomOperand Op>
1177-
: OperandWithDefaultOps<Op.Type, (ops (Op.Type 0))>,
1168+
class DefaultOperand<CustomOperand Op, int Value>
1169+
: OperandWithDefaultOps<Op.Type, (ops (Op.Type Value))>,
11781170
CustomOperandProps<1, Op.ParserMatchClass.Name, Op.ParserMatchClass>;
11791171

1180-
class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
1181-
let PrintMethod = "print"#Name;
1182-
let ParserMatchClass = MatchClass;
1183-
}
1184-
1185-
class NamedOperandU32_0<string Name, AsmOperandClass MatchClass> :
1186-
OperandWithDefaultOps<i32, (ops (i32 0))> {
1187-
let PrintMethod = "print"#Name;
1188-
let ParserMatchClass = MatchClass;
1189-
}
1190-
1191-
class NamedOperandU32Default0<string Name, AsmOperandClass MatchClass> :
1192-
OperandWithDefaultOps<i32, (ops (i32 0))> {
1193-
let PrintMethod = "print"#Name;
1194-
let ParserMatchClass = MatchClass;
1195-
}
1196-
1197-
class NamedOperandU32Default1<string Name, AsmOperandClass MatchClass> :
1198-
OperandWithDefaultOps<i32, (ops (i32 1))> {
1199-
let PrintMethod = "print"#Name;
1200-
let ParserMatchClass = MatchClass;
1201-
}
1202-
12031172
class SDWAOperandClass<string Id, string Name>
12041173
: CustomOperandClass<Name, 1> {
12051174
string ImmTy = "AMDGPUOperand::ImmTy"#Name;
@@ -1211,7 +1180,17 @@ class SDWAOperandClass<string Id, string Name>
12111180
class SDWAOperand<string Id, string Name = NAME>
12121181
: CustomOperand<i32, 1, Name, SDWAOperandClass<Id, Name>>;
12131182

1214-
let OperandType = "OPERAND_IMMEDIATE" in {
1183+
class ArrayOperandClass<string Id, string Name>
1184+
: CustomOperandClass<Name, 1> {
1185+
string ImmTy = "AMDGPUOperand::ImmTy"#Name;
1186+
let ParserMethod =
1187+
"[this](OperandVector &Operands) -> OperandMatchResultTy { "#
1188+
"return parseOperandArrayWithPrefix(\""#Id#"\", Operands, "#ImmTy#"); }";
1189+
}
1190+
1191+
class ArrayOperand0<string Id, string Name = NAME>
1192+
: OperandWithDefaultOps<i32, (ops (i32 0))>,
1193+
CustomOperandProps<1, Name, ArrayOperandClass<Id, Name>>;
12151194

12161195
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
12171196
def offset : NamedIntOperand<i32, "offset", "Offset">;
@@ -1220,23 +1199,23 @@ def offset1 : NamedIntOperand<i8, "offset1", "Offset1">;
12201199

12211200
def gds : NamedBitOperand<"gds", "GDS">;
12221201

1223-
def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
1224-
def omod0 : NamedOperandU32_0<"OModSI", NamedMatchClass<"OModSI">>;
1202+
def omod : CustomOperand<i32, 1, "OModSI">;
1203+
def omod0 : DefaultOperand<omod, 0>;
12251204

12261205
// We need to make the cases with a default of 0 distinct from no
12271206
// default to help deal with some cases where the operand appears
12281207
// before a mandatory operand.
12291208
def clampmod : NamedBitOperand<"clamp", "ClampSI">;
1230-
def clampmod0 : DefaultOperand_0<clampmod>;
1209+
def clampmod0 : DefaultOperand<clampmod, 0>;
12311210
def highmod : NamedBitOperand<"high", "High">;
12321211

1233-
def CPol : NamedOperandU32<"CPol", NamedMatchClass<"CPol">>;
1234-
def CPol_0 : NamedOperandU32Default0<"CPol", NamedMatchClass<"CPol">>;
1235-
def CPol_GLC1 : NamedOperandU32Default1<"CPol", NamedMatchClass<"CPol">>;
1212+
def CPol : CustomOperand<i32, 1>;
1213+
def CPol_0 : DefaultOperand<CPol, 0>;
1214+
def CPol_GLC1 : DefaultOperand<CPol, 1>;
12361215

12371216
def TFE : NamedBitOperand<"tfe">;
12381217
def SWZ : NamedBitOperand<"swz">;
1239-
def SWZ_0 : DefaultOperand_0<SWZ>;
1218+
def SWZ_0 : DefaultOperand<SWZ, 0>;
12401219
def UNorm : NamedBitOperand<"unorm">;
12411220
def DA : NamedBitOperand<"da">;
12421221
def R128A16 : CustomOperand<i1, 1>;
@@ -1256,10 +1235,10 @@ def src0_sel : SDWAOperand<"src0_sel", "SDWASrc0Sel">;
12561235
def src1_sel : SDWAOperand<"src1_sel", "SDWASrc1Sel">;
12571236
def dst_unused : CustomOperand<i32, 1, "SDWADstUnused">;
12581237

1259-
def op_sel0 : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>;
1260-
def op_sel_hi0 : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>;
1261-
def neg_lo0 : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
1262-
def neg_hi0 : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
1238+
def op_sel0 : ArrayOperand0<"op_sel", "OpSel">;
1239+
def op_sel_hi0 : ArrayOperand0<"op_sel_hi", "OpSelHi">;
1240+
def neg_lo0 : ArrayOperand0<"neg_lo", "NegLo">;
1241+
def neg_hi0 : ArrayOperand0<"neg_hi", "NegHi">;
12631242

12641243
def dpp8 : CustomOperand<i32, 0, "DPP8">;
12651244
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;
@@ -1281,8 +1260,6 @@ def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
12811260
def wait_vdst : NamedIntOperand<i8, "wait_vdst", "WaitVDST">;
12821261
def wait_exp : NamedIntOperand<i8, "wait_exp", "WaitEXP">;
12831262

1284-
} // End OperandType = "OPERAND_IMMEDIATE"
1285-
12861263
class KImmMatchClass<int size> : AsmOperandClass {
12871264
let Name = "KImmFP"#size;
12881265
let PredicateMethod = "isKImmFP"#size;

llvm/lib/Target/AMDGPU/SMInstructions.td

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,7 @@
88

99
def smrd_offset_8 : ImmOperand<i32, "SMRDOffset8", 1>;
1010

11-
let OperandType = "OPERAND_IMMEDIATE",
12-
EncoderMethod = "getSMEMOffsetEncoding",
11+
let EncoderMethod = "getSMEMOffsetEncoding",
1312
DecoderMethod = "decodeSMEMOffset" in {
1413
def smem_offset : ImmOperand<i32, "SMEMOffset", 1>;
1514
def smem_offset_mod : NamedIntOperand<i32, "offset", "SMEMOffsetMod">;

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