Skip to content

Commit a71dc1b

Browse files
committed
Addressed the reviewed changes.
1 parent daa3d16 commit a71dc1b

File tree

6 files changed

+10
-14
lines changed

6 files changed

+10
-14
lines changed

llvm/include/llvm/CodeGen/LiveRegUnits.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ class LiveRegUnits {
9090

9191
/// Adds register units covered by physical register \p Reg that are
9292
/// part of the lanemask \p Mask.
93-
void addRegMasked(MCRegister Reg, LaneBitmask Mask) {
93+
void addRegMasked(MCRegister Reg, LaneBitmask Mask = LaneBitmask::getAll()) {
9494
for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
9595
LaneBitmask UnitMask = (*Unit).second;
9696
if ((UnitMask & Mask).any())

llvm/include/llvm/CodeGen/MachineBasicBlock.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@
1313
#ifndef LLVM_CODEGEN_MACHINEBASICBLOCK_H
1414
#define LLVM_CODEGEN_MACHINEBASICBLOCK_H
1515

16-
#include "llvm/ADT/BitVector.h"
1716
#include "llvm/ADT/DenseMapInfo.h"
1817
#include "llvm/ADT/DenseSet.h"
1918
#include "llvm/ADT/GraphTraits.h"

llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,9 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
6767
for (const MachineBasicBlock *Succ : BB->successors())
6868
for (const auto &LI : Succ->liveins()) {
6969
for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
70-
unsigned Reg = (*AI).id();
71-
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
72-
KillIndices[Reg] = BBSize;
70+
MCRegister Reg = *AI;
71+
Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1);
72+
KillIndices[Reg.id()] = BBSize;
7373
DefIndices[Reg] = ~0u;
7474
}
7575
}

llvm/lib/CodeGen/LiveRegUnits.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ void LiveRegUnits::accumulate(const MachineInstr &MI) {
8888
static void addBlockLiveIns(LiveRegUnits &LiveUnits,
8989
const MachineBasicBlock &MBB) {
9090
for (const auto &LI : MBB.liveins())
91-
LiveUnits.addRegMasked(LI, LaneBitmask::getAll());
91+
LiveUnits.addRegMasked(LI);
9292
}
9393

9494
/// Adds all callee saved registers to \p LiveUnits.

llvm/lib/CodeGen/MIRPrinter.cpp

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -728,12 +728,9 @@ void printMBB(raw_ostream &OS, MFPrintState &State,
728728
if (!MBB.livein_empty()) {
729729
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
730730
OS.indent(2) << "liveins: ";
731-
bool First = true;
732-
for (const Register Reg : MBB.liveins_dbg()) {
733-
if (!First)
734-
OS << ", ";
735-
First = false;
736-
OS << printReg(Reg, &TRI);
731+
ListSeparator LS;
732+
for (const auto &LI : MBB.liveins_dbg()) {
733+
OS << LS << printReg(LI, &TRI);
737734
}
738735
OS << "\n";
739736
HasLineAttributes = true;

llvm/lib/CodeGen/MachineBasicBlock.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -427,7 +427,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
427427
OS.indent(2) << "liveins: ";
428428

429429
ListSeparator LS;
430-
for (const MCRegister Reg : liveins()) {
430+
for (MCRegister Reg : liveins()) {
431431
OS << LS << printReg(Reg, TRI);
432432
}
433433
HasLineAttributes = true;
@@ -656,7 +656,7 @@ bool MachineBasicBlock::isLiveIn(MCRegister Reg, LaneBitmask LaneMask) const {
656656
Register
657657
MachineBasicBlock::addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC) {
658658
assert(getParent() && "MBB must be inserted in function");
659-
assert(PhysReg && "Expected physreg");
659+
assert(PhysReg.isPhysical() && "Expected physreg");
660660
assert(RC && "Register class is required");
661661
assert((isEHPad() || this == &getParent()->front()) &&
662662
"Only the entry block and landing pads can have physreg live ins");

0 commit comments

Comments
 (0)