resolve comment

Author: XinWang10

llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp

@@ -1135,11 +1135,11 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID,
 }
 
 static bool isNF(InternalInstruction *insn) {
-  // NF bit is the MSB of aaa.
-  if (nfFromEVEX4of4(insn->vectorExtensionPrefix[3]) &&
-      insn->opcodeType == MAP4)
+  if (!nfFromEVEX4of4(insn->vectorExtensionPrefix[3]))
+    return false;
+  if (insn->opcodeType == MAP4)
     return true;
-  // Promoted BMI instrs below has nf version but not in map4.
+  // Below NF instructions are not in map4.
   if (insn->opcodeType == THREEBYTE_38 &&
       ppFromEVEX3of4(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) {
     switch (insn->opcode) {
@@ -1148,6 +1148,8 @@ static bool isNF(InternalInstruction *insn) {
     case 0xf5: // BZHI
     case 0xf7: // BEXTR
       return true;
+    default:
+      break;
     }
   }
   return false;
@@ -1188,7 +1190,7 @@ static int getInstructionID(struct InternalInstruction *insn,
         attrMask |= ATTR_EVEXKZ;
       if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
         attrMask |= ATTR_EVEXB;
-      if (isNF(insn))
+      if (isNF(insn)) // NF bit is the MSB of aaa.
         attrMask |= ATTR_EVEXNF;
       else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
         attrMask |= ATTR_EVEXK;

llvm/lib/Target/X86/X86InstrArithmetic.td

@@ -1030,7 +1030,7 @@ def : Pat<(X86testpat (loadi64 addr:$src1), i64relocImmSExt32_su:$src2),
 //===----------------------------------------------------------------------===//
 // ANDN Instruction
 //
-multiclass AndN<X86TypeInfo t, string suffix> {
+multiclass AndN<X86TypeInfo t, string suffix = ""> {
   defvar andn_rr_p =
     [(set t.RegClass:$dst, EFLAGS, (X86and_flag (not t.RegClass:$src1),
      t.RegClass:$src2))];
@@ -1050,8 +1050,8 @@ multiclass AndN<X86TypeInfo t, string suffix> {
 
 // Complexity is reduced to give and with immediate a chance to match first.
 let AddedComplexity = -6 in {
-defm ANDN32 : AndN<Xi32, "">, VEX, Requires<[HasBMI, NoEGPR]>;
-defm ANDN64 : AndN<Xi64, "">, VEX, REX_W, Requires<[HasBMI, NoEGPR]>;
+defm ANDN32 : AndN<Xi32>, VEX, Requires<[HasBMI, NoEGPR]>;
+defm ANDN64 : AndN<Xi64>, VEX, REX_W, Requires<[HasBMI, NoEGPR]>;
 defm ANDN32 : AndN<Xi32, "_EVEX">, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>;
 defm ANDN64 : AndN<Xi64, "_EVEX">, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>;
 let Pattern = [(null_frag)] in {