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[Xtensa] Implement Xtensa S32C1I Option and atomics lowering.
Implement Xtensa S32C1I Option and use s32c1i instruction to implement atomics operations.
1 parent 8676027 commit b127324

13 files changed

+7628
-35
lines changed

‎llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp‎

Lines changed: 34 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -145,39 +145,40 @@ struct DecodeRegister {
145145
};
146146

147147
const DecodeRegister SRDecoderTable[] = {
148-
{Xtensa::LBEG, 0}, {Xtensa::LEND, 1},
149-
{Xtensa::LCOUNT, 2}, {Xtensa::SAR, 3},
150-
{Xtensa::BREG, 4}, {Xtensa::LITBASE, 5},
151-
{Xtensa::ACCLO, 16}, {Xtensa::ACCHI, 17},
152-
{Xtensa::M0, 32}, {Xtensa::M1, 33},
153-
{Xtensa::M2, 34}, {Xtensa::M3, 35},
154-
{Xtensa::WINDOWBASE, 72}, {Xtensa::WINDOWSTART, 73},
155-
{Xtensa::IBREAKENABLE, 96}, {Xtensa::MEMCTL, 97},
156-
{Xtensa::DDR, 104}, {Xtensa::IBREAKA0, 128},
157-
{Xtensa::IBREAKA1, 129}, {Xtensa::DBREAKA0, 144},
158-
{Xtensa::DBREAKA1, 145}, {Xtensa::DBREAKC0, 160},
159-
{Xtensa::DBREAKC1, 161}, {Xtensa::CONFIGID0, 176},
160-
{Xtensa::EPC1, 177}, {Xtensa::EPC2, 178},
161-
{Xtensa::EPC3, 179}, {Xtensa::EPC4, 180},
162-
{Xtensa::EPC5, 181}, {Xtensa::EPC6, 182},
163-
{Xtensa::EPC7, 183}, {Xtensa::DEPC, 192},
164-
{Xtensa::EPS2, 194}, {Xtensa::EPS3, 195},
165-
{Xtensa::EPS4, 196}, {Xtensa::EPS5, 197},
166-
{Xtensa::EPS6, 198}, {Xtensa::EPS7, 199},
167-
{Xtensa::CONFIGID1, 208}, {Xtensa::EXCSAVE1, 209},
168-
{Xtensa::EXCSAVE2, 210}, {Xtensa::EXCSAVE3, 211},
169-
{Xtensa::EXCSAVE4, 212}, {Xtensa::EXCSAVE5, 213},
170-
{Xtensa::EXCSAVE6, 214}, {Xtensa::EXCSAVE7, 215},
171-
{Xtensa::CPENABLE, 224}, {Xtensa::INTERRUPT, 226},
172-
{Xtensa::INTCLEAR, 227}, {Xtensa::INTENABLE, 228},
173-
{Xtensa::PS, 230}, {Xtensa::VECBASE, 231},
174-
{Xtensa::EXCCAUSE, 232}, {Xtensa::DEBUGCAUSE, 233},
175-
{Xtensa::CCOUNT, 234}, {Xtensa::PRID, 235},
176-
{Xtensa::ICOUNT, 236}, {Xtensa::ICOUNTLEVEL, 237},
177-
{Xtensa::EXCVADDR, 238}, {Xtensa::CCOMPARE0, 240},
178-
{Xtensa::CCOMPARE1, 241}, {Xtensa::CCOMPARE2, 242},
179-
{Xtensa::MISC0, 244}, {Xtensa::MISC1, 245},
180-
{Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}};
148+
{Xtensa::LBEG, 0}, {Xtensa::LEND, 1},
149+
{Xtensa::LCOUNT, 2}, {Xtensa::SAR, 3},
150+
{Xtensa::BREG, 4}, {Xtensa::LITBASE, 5},
151+
{Xtensa::SCOMPARE1, 12}, {Xtensa::ACCLO, 16},
152+
{Xtensa::ACCHI, 17}, {Xtensa::M0, 32},
153+
{Xtensa::M1, 33}, {Xtensa::M2, 34},
154+
{Xtensa::M3, 35}, {Xtensa::WINDOWBASE, 72},
155+
{Xtensa::WINDOWSTART, 73}, {Xtensa::IBREAKENABLE, 96},
156+
{Xtensa::MEMCTL, 97}, {Xtensa::ATOMCTL, 99},
157+
{Xtensa::DDR, 104}, {Xtensa::IBREAKA0, 128},
158+
{Xtensa::IBREAKA1, 129}, {Xtensa::DBREAKA0, 144},
159+
{Xtensa::DBREAKA1, 145}, {Xtensa::DBREAKC0, 160},
160+
{Xtensa::DBREAKC1, 161}, {Xtensa::CONFIGID0, 176},
161+
{Xtensa::EPC1, 177}, {Xtensa::EPC2, 178},
162+
{Xtensa::EPC3, 179}, {Xtensa::EPC4, 180},
163+
{Xtensa::EPC5, 181}, {Xtensa::EPC6, 182},
164+
{Xtensa::EPC7, 183}, {Xtensa::DEPC, 192},
165+
{Xtensa::EPS2, 194}, {Xtensa::EPS3, 195},
166+
{Xtensa::EPS4, 196}, {Xtensa::EPS5, 197},
167+
{Xtensa::EPS6, 198}, {Xtensa::EPS7, 199},
168+
{Xtensa::CONFIGID1, 208}, {Xtensa::EXCSAVE1, 209},
169+
{Xtensa::EXCSAVE2, 210}, {Xtensa::EXCSAVE3, 211},
170+
{Xtensa::EXCSAVE4, 212}, {Xtensa::EXCSAVE5, 213},
171+
{Xtensa::EXCSAVE6, 214}, {Xtensa::EXCSAVE7, 215},
172+
{Xtensa::CPENABLE, 224}, {Xtensa::INTERRUPT, 226},
173+
{Xtensa::INTCLEAR, 227}, {Xtensa::INTENABLE, 228},
174+
{Xtensa::PS, 230}, {Xtensa::VECBASE, 231},
175+
{Xtensa::EXCCAUSE, 232}, {Xtensa::DEBUGCAUSE, 233},
176+
{Xtensa::CCOUNT, 234}, {Xtensa::PRID, 235},
177+
{Xtensa::ICOUNT, 236}, {Xtensa::ICOUNTLEVEL, 237},
178+
{Xtensa::EXCVADDR, 238}, {Xtensa::CCOMPARE0, 240},
179+
{Xtensa::CCOMPARE1, 241}, {Xtensa::CCOMPARE2, 242},
180+
{Xtensa::MISC0, 244}, {Xtensa::MISC1, 245},
181+
{Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}};
181182

182183
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
183184
uint64_t Address,

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -200,6 +200,9 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits,
200200
case Xtensa::WINDOWBASE:
201201
case Xtensa::WINDOWSTART:
202202
return FeatureBits[Xtensa::FeatureWindowed];
203+
case Xtensa::ATOMCTL:
204+
case Xtensa::SCOMPARE1:
205+
return FeatureBits[Xtensa::FeatureWindowed];
203206
case Xtensa::NoRegister:
204207
return false;
205208
}

‎llvm/lib/Target/Xtensa/XtensaFeatures.td‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,22 @@ def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
7373
def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
7474
AssemblerPredicate<(all_of FeatureDiv32)>;
7575

76+
def FeatureS32C1I : SubtargetFeature<"s32c1i", "HasS32C1I", "true",
77+
"Enable Xtensa S32C1I option">;
78+
def HasS32C1I : Predicate<"Subtarget->hasS32C1I()">,
79+
AssemblerPredicate<(all_of FeatureS32C1I)>;
80+
81+
// Assume that lock-free native-width atomics are available, even if the target
82+
// and operating system combination would not usually provide them. The user
83+
// is responsible for providing any necessary __sync implementations. Code
84+
// built with this feature is not ABI-compatible with code built without this
85+
// feature, if atomic variables are exposed across the ABI boundary.
86+
def FeatureForcedAtomics : SubtargetFeature<"forced-atomics", "HasForcedAtomics", "true",
87+
"Assume that lock-free native-width atomics are available">;
88+
def HasForcedAtomics : Predicate<"Subtarget->hasForcedAtomics()">,
89+
AssemblerPredicate<(all_of FeatureForcedAtomics)>;
90+
def HasAtomicLdSt : Predicate<"Subtarget->hasS32C1I() || Subtarget->hasForcedAtomics()">;
91+
7692
def FeatureRegionProtection : SubtargetFeature<"regprotect", "HasRegionProtection", "true",
7793
"Enable Xtensa Region Protection option">;
7894
def HasRegionProtection : Predicate<"Subtarget->hasRegionProtection()">,

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