Skip to content

Commit b4729f7

Browse files
lukel97lukel97
authored
[RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (#66659)
We currently shrink the type of vmv_s_x_vl to LMUL=1 when its passthru is undef to avoid constraining the register allocator since it ignores LMUL. This patch relaxes it for non-undef passthrus, which occurs when lowering insert_vector_elt.
1 parent 78a8878 commit b4729f7

File tree

3 files changed

+28
-25
lines changed

3 files changed

+28
-25
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+7-4
Original file line numberDiff line numberDiff line change
@@ -14942,11 +14942,14 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1494214942

1494314943
// Use M1 or smaller to avoid over constraining register allocation
1494414944
const MVT M1VT = getLMUL1VT(VT);
14945-
if (M1VT.bitsLT(VT) && Passthru.isUndef()) {
14945+
if (M1VT.bitsLT(VT)) {
14946+
SDValue M1Passthru =
14947+
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Passthru,
14948+
DAG.getVectorIdxConstant(0, DL));
1494614949
SDValue Result =
14947-
DAG.getNode(N->getOpcode(), DL, M1VT, Passthru, Scalar, VL);
14948-
Result = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT),
14949-
Result, DAG.getConstant(0, DL, XLenVT));
14950+
DAG.getNode(N->getOpcode(), DL, M1VT, M1Passthru, Scalar, VL);
14951+
Result = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Passthru, Result,
14952+
DAG.getConstant(0, DL, XLenVT));
1495014953
return Result;
1495114954
}
1495214955

‎llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll

+9-9
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ declare <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8>, i8, i
5858
define <vscale x 16 x i8> @intrinsic_vmv.s.x_x_nxv16i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
5959
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i8:
6060
; CHECK: # %bb.0: # %entry
61-
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, ma
61+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
6262
; CHECK-NEXT: vmv.s.x v8, a0
6363
; CHECK-NEXT: ret
6464
entry:
@@ -71,7 +71,7 @@ declare <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8>, i8, i
7171
define <vscale x 32 x i8> @intrinsic_vmv.s.x_x_nxv32i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
7272
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i8:
7373
; CHECK: # %bb.0: # %entry
74-
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, ma
74+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
7575
; CHECK-NEXT: vmv.s.x v8, a0
7676
; CHECK-NEXT: ret
7777
entry:
@@ -84,7 +84,7 @@ declare <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8>, i8, i
8484
define <vscale x 64 x i8> @intrinsic_vmv.s.x_x_nxv64i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
8585
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv64i8:
8686
; CHECK: # %bb.0: # %entry
87-
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
87+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
8888
; CHECK-NEXT: vmv.s.x v8, a0
8989
; CHECK-NEXT: ret
9090
entry:
@@ -136,7 +136,7 @@ declare <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16>, i16,
136136
define <vscale x 8 x i16> @intrinsic_vmv.s.x_x_nxv8i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
137137
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i16:
138138
; CHECK: # %bb.0: # %entry
139-
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, ma
139+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
140140
; CHECK-NEXT: vmv.s.x v8, a0
141141
; CHECK-NEXT: ret
142142
entry:
@@ -149,7 +149,7 @@ declare <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16>, i1
149149
define <vscale x 16 x i16> @intrinsic_vmv.s.x_x_nxv16i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
150150
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i16:
151151
; CHECK: # %bb.0: # %entry
152-
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma
152+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
153153
; CHECK-NEXT: vmv.s.x v8, a0
154154
; CHECK-NEXT: ret
155155
entry:
@@ -162,7 +162,7 @@ declare <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16>, i1
162162
define <vscale x 32 x i16> @intrinsic_vmv.s.x_x_nxv32i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
163163
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i16:
164164
; CHECK: # %bb.0: # %entry
165-
; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, ma
165+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
166166
; CHECK-NEXT: vmv.s.x v8, a0
167167
; CHECK-NEXT: ret
168168
entry:
@@ -201,7 +201,7 @@ declare <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32>, i32,
201201
define <vscale x 4 x i32> @intrinsic_vmv.s.x_x_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
202202
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i32:
203203
; CHECK: # %bb.0: # %entry
204-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
204+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
205205
; CHECK-NEXT: vmv.s.x v8, a0
206206
; CHECK-NEXT: ret
207207
entry:
@@ -214,7 +214,7 @@ declare <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32>, i32,
214214
define <vscale x 8 x i32> @intrinsic_vmv.s.x_x_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
215215
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i32:
216216
; CHECK: # %bb.0: # %entry
217-
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
217+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
218218
; CHECK-NEXT: vmv.s.x v8, a0
219219
; CHECK-NEXT: ret
220220
entry:
@@ -227,7 +227,7 @@ declare <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32>, i3
227227
define <vscale x 16 x i32> @intrinsic_vmv.s.x_x_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
228228
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32:
229229
; CHECK: # %bb.0: # %entry
230-
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
230+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
231231
; CHECK-NEXT: vmv.s.x v8, a0
232232
; CHECK-NEXT: ret
233233
entry:

‎llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll

+12-12
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ declare <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8>, i8, i
5858
define <vscale x 16 x i8> @intrinsic_vmv.s.x_x_nxv16i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
5959
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i8:
6060
; CHECK: # %bb.0: # %entry
61-
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, ma
61+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
6262
; CHECK-NEXT: vmv.s.x v8, a0
6363
; CHECK-NEXT: ret
6464
entry:
@@ -71,7 +71,7 @@ declare <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8>, i8, i
7171
define <vscale x 32 x i8> @intrinsic_vmv.s.x_x_nxv32i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
7272
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i8:
7373
; CHECK: # %bb.0: # %entry
74-
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, ma
74+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
7575
; CHECK-NEXT: vmv.s.x v8, a0
7676
; CHECK-NEXT: ret
7777
entry:
@@ -84,7 +84,7 @@ declare <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8>, i8, i
8484
define <vscale x 64 x i8> @intrinsic_vmv.s.x_x_nxv64i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
8585
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv64i8:
8686
; CHECK: # %bb.0: # %entry
87-
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
87+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
8888
; CHECK-NEXT: vmv.s.x v8, a0
8989
; CHECK-NEXT: ret
9090
entry:
@@ -136,7 +136,7 @@ declare <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16>, i16,
136136
define <vscale x 8 x i16> @intrinsic_vmv.s.x_x_nxv8i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
137137
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i16:
138138
; CHECK: # %bb.0: # %entry
139-
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, ma
139+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
140140
; CHECK-NEXT: vmv.s.x v8, a0
141141
; CHECK-NEXT: ret
142142
entry:
@@ -149,7 +149,7 @@ declare <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16>, i1
149149
define <vscale x 16 x i16> @intrinsic_vmv.s.x_x_nxv16i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
150150
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i16:
151151
; CHECK: # %bb.0: # %entry
152-
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma
152+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
153153
; CHECK-NEXT: vmv.s.x v8, a0
154154
; CHECK-NEXT: ret
155155
entry:
@@ -162,7 +162,7 @@ declare <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16>, i1
162162
define <vscale x 32 x i16> @intrinsic_vmv.s.x_x_nxv32i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
163163
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i16:
164164
; CHECK: # %bb.0: # %entry
165-
; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, ma
165+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
166166
; CHECK-NEXT: vmv.s.x v8, a0
167167
; CHECK-NEXT: ret
168168
entry:
@@ -201,7 +201,7 @@ declare <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32>, i32,
201201
define <vscale x 4 x i32> @intrinsic_vmv.s.x_x_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
202202
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i32:
203203
; CHECK: # %bb.0: # %entry
204-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
204+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
205205
; CHECK-NEXT: vmv.s.x v8, a0
206206
; CHECK-NEXT: ret
207207
entry:
@@ -214,7 +214,7 @@ declare <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32>, i32,
214214
define <vscale x 8 x i32> @intrinsic_vmv.s.x_x_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
215215
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i32:
216216
; CHECK: # %bb.0: # %entry
217-
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
217+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
218218
; CHECK-NEXT: vmv.s.x v8, a0
219219
; CHECK-NEXT: ret
220220
entry:
@@ -227,7 +227,7 @@ declare <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32>, i3
227227
define <vscale x 16 x i32> @intrinsic_vmv.s.x_x_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
228228
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32:
229229
; CHECK: # %bb.0: # %entry
230-
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
230+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
231231
; CHECK-NEXT: vmv.s.x v8, a0
232232
; CHECK-NEXT: ret
233233
entry:
@@ -253,7 +253,7 @@ declare <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64>, i64,
253253
define <vscale x 2 x i64> @intrinsic_vmv.s.x_x_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
254254
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i64:
255255
; CHECK: # %bb.0: # %entry
256-
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, ma
256+
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, ma
257257
; CHECK-NEXT: vmv.s.x v8, a0
258258
; CHECK-NEXT: ret
259259
entry:
@@ -266,7 +266,7 @@ declare <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64>, i64,
266266
define <vscale x 4 x i64> @intrinsic_vmv.s.x_x_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
267267
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i64:
268268
; CHECK: # %bb.0: # %entry
269-
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, ma
269+
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, ma
270270
; CHECK-NEXT: vmv.s.x v8, a0
271271
; CHECK-NEXT: ret
272272
entry:
@@ -279,7 +279,7 @@ declare <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64>, i64,
279279
define <vscale x 8 x i64> @intrinsic_vmv.s.x_x_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
280280
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i64:
281281
; CHECK: # %bb.0: # %entry
282-
; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma
282+
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, ma
283283
; CHECK-NEXT: vmv.s.x v8, a0
284284
; CHECK-NEXT: ret
285285
entry:

0 commit comments

Comments
 (0)