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[AMDGPU][AsmParser][NFC] Simplify parsing of sopp_brtarget operands.
Also refine the definitions while there. Part of <#62629>. Reviewed By: mbrkusanin Differential Revision: https://reviews.llvm.org/D154061
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+29
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 10 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -858,9 +858,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
858858
return Kind == Expression;
859859
}
860860

861-
bool isSoppBrTarget() const {
862-
return isExpr() || isImm();
863-
}
861+
bool isSOPPBrTarget() const { return isExpr() || isImm(); }
864862

865863
bool isSWaitCnt() const;
866864
bool isDepCtr() const;
@@ -971,8 +969,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
971969
void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
972970
if (isRegKind())
973971
addRegOperands(Inst, N);
974-
else if (isExpr())
975-
Inst.addOperand(MCOperand::createExpr(Expr));
976972
else
977973
addImmOperands(Inst, N);
978974
}
@@ -1014,15 +1010,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
10141010
addRegWithInputModsOperands(Inst, N);
10151011
}
10161012

1017-
void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const {
1018-
if (isImm())
1019-
addImmOperands(Inst, N);
1020-
else {
1021-
assert(isExpr());
1022-
Inst.addOperand(MCOperand::createExpr(Expr));
1023-
}
1024-
}
1025-
10261013
static void printImmTy(raw_ostream& OS, ImmTy Type) {
10271014
switch (Type) {
10281015
case ImmTyNone: OS << "None"; break;
@@ -1726,7 +1713,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17261713
OperandMatchResultTy parseSendMsg(OperandVector &Operands);
17271714
OperandMatchResultTy parseInterpSlot(OperandVector &Operands);
17281715
OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
1729-
OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
1716+
OperandMatchResultTy parseSOPPBrTarget(OperandVector &Operands);
17301717
OperandMatchResultTy parseBoolReg(OperandVector &Operands);
17311718

17321719
bool parseSwizzleOperand(int64_t &Op,
@@ -2084,6 +2071,11 @@ uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const
20842071
}
20852072

20862073
void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {
2074+
if (isExpr()) {
2075+
Inst.addOperand(MCOperand::createExpr(Expr));
2076+
return;
2077+
}
2078+
20872079
if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
20882080
Inst.getNumOperands())) {
20892081
addLiteralImmOperand(Inst, Imm.Val,
@@ -7674,7 +7666,7 @@ bool AMDGPUOperand::isGPRIdxMode() const {
76747666
//===----------------------------------------------------------------------===//
76757667

76767668
OperandMatchResultTy
7677-
AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
7669+
AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {
76787670

76797671
// Make sure we are not parsing something
76807672
// that looks like a label or an expression but is not.
@@ -9052,8 +9044,8 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
90529044
return Operand.isSSrcB32() ? Match_Success : Match_InvalidOperand;
90539045
case MCK_SSrcF32:
90549046
return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;
9055-
case MCK_SoppBrTarget:
9056-
return Operand.isSoppBrTarget() ? Match_Success : Match_InvalidOperand;
9047+
case MCK_SOPPBrTarget:
9048+
return Operand.isSOPPBrTarget() ? Match_Success : Match_InvalidOperand;
90579049
case MCK_VReg32OrOff:
90589050
return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;
90599051
case MCK_InterpSlot:

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
7474
return OpIdx;
7575
}
7676

77-
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
77+
static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm,
7878
uint64_t Addr,
7979
const MCDisassembler *Decoder) {
8080
auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -921,16 +921,11 @@ def set_glc : SDNodeXForm<timm, [{
921921
// Custom Operands
922922
//===----------------------------------------------------------------------===//
923923

924-
def SoppBrTarget : AsmOperandClass {
925-
let Name = "SoppBrTarget";
926-
let ParserMethod = "parseSOppBrTarget";
927-
}
928-
929-
def sopp_brtarget : Operand<OtherVT> {
924+
def SOPPBrTarget : CustomOperand<OtherVT> {
925+
let PrintMethod = "printOperand";
930926
let EncoderMethod = "getSOPPBrEncoding";
931-
let DecoderMethod = "decodeSoppBrTarget";
927+
let DecoderMethod = "decodeSOPPBrTarget";
932928
let OperandType = "OPERAND_PCREL";
933-
let ParserMatchClass = SoppBrTarget;
934929
}
935930

936931
def si_ga : Operand<iPTR>;

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -500,7 +500,7 @@ def SI_ILLEGAL_COPY : SPseudoInstSI <
500500

501501
// Branch on undef scc. Used to avoid intermediate copy from
502502
// IMPLICIT_DEF to SCC.
503-
def SI_BR_UNDEF : SPseudoInstSI <(outs), (ins sopp_brtarget:$simm16)> {
503+
def SI_BR_UNDEF : SPseudoInstSI <(outs), (ins SOPPBrTarget:$simm16)> {
504504
let isTerminator = 1;
505505
let usesCustomInserter = 1;
506506
let isBranch = 1;

‎llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -784,7 +784,7 @@ class SOPK_32 <string opName, list<dag> pattern=[]> : SOPK_Pseudo <
784784
class SOPK_32_BR <string opName, list<dag> pattern=[]> : SOPK_Pseudo <
785785
opName,
786786
(outs),
787-
(ins sopp_brtarget:$simm16, SReg_32:$sdst),
787+
(ins SOPPBrTarget:$simm16, SReg_32:$sdst),
788788
"$sdst, $simm16",
789789
pattern> {
790790
let Defs = [EXEC];
@@ -864,7 +864,7 @@ let isCommutable = 1, DisableEncoding = "$src0",
864864
let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in
865865
def S_CBRANCH_I_FORK : SOPK_Pseudo <
866866
"s_cbranch_i_fork",
867-
(outs), (ins SReg_64:$sdst, sopp_brtarget:$simm16),
867+
(outs), (ins SReg_64:$sdst, SOPPBrTarget:$simm16),
868868
"$sdst, $simm16"
869869
>;
870870

@@ -942,7 +942,7 @@ let SubtargetPredicate = isGFX9Plus in {
942942
def S_CALL_B64 : SOPK_Pseudo<
943943
"s_call_b64",
944944
(outs SReg_64:$sdst),
945-
(ins sopp_brtarget:$simm16),
945+
(ins SOPPBrTarget:$simm16),
946946
"$sdst, $simm16"> {
947947
let isCall = 1;
948948
}
@@ -1195,60 +1195,60 @@ let SubtargetPredicate = isGFX10Plus in {
11951195
let isBranch = 1, SchedRW = [WriteBranch] in {
11961196
let isBarrier = 1 in {
11971197
defm S_BRANCH : SOPP_With_Relaxation<
1198-
"s_branch" , (ins sopp_brtarget:$simm16), "$simm16",
1198+
"s_branch" , (ins SOPPBrTarget:$simm16), "$simm16",
11991199
[(br bb:$simm16)]>;
12001200
}
12011201

12021202
let Uses = [SCC] in {
12031203
defm S_CBRANCH_SCC0 : SOPP_With_Relaxation<
1204-
"s_cbranch_scc0" , (ins sopp_brtarget:$simm16),
1204+
"s_cbranch_scc0" , (ins SOPPBrTarget:$simm16),
12051205
"$simm16"
12061206
>;
12071207
defm S_CBRANCH_SCC1 : SOPP_With_Relaxation <
1208-
"s_cbranch_scc1" , (ins sopp_brtarget:$simm16),
1208+
"s_cbranch_scc1" , (ins SOPPBrTarget:$simm16),
12091209
"$simm16"
12101210
>;
12111211
} // End Uses = [SCC]
12121212

12131213
let Uses = [VCC] in {
12141214
defm S_CBRANCH_VCCZ : SOPP_With_Relaxation <
1215-
"s_cbranch_vccz" , (ins sopp_brtarget:$simm16),
1215+
"s_cbranch_vccz" , (ins SOPPBrTarget:$simm16),
12161216
"$simm16"
12171217
>;
12181218
defm S_CBRANCH_VCCNZ : SOPP_With_Relaxation <
1219-
"s_cbranch_vccnz" , (ins sopp_brtarget:$simm16),
1219+
"s_cbranch_vccnz" , (ins SOPPBrTarget:$simm16),
12201220
"$simm16"
12211221
>;
12221222
} // End Uses = [VCC]
12231223

12241224
let Uses = [EXEC] in {
12251225
defm S_CBRANCH_EXECZ : SOPP_With_Relaxation <
1226-
"s_cbranch_execz" , (ins sopp_brtarget:$simm16),
1226+
"s_cbranch_execz" , (ins SOPPBrTarget:$simm16),
12271227
"$simm16"
12281228
>;
12291229
defm S_CBRANCH_EXECNZ : SOPP_With_Relaxation <
1230-
"s_cbranch_execnz" , (ins sopp_brtarget:$simm16),
1230+
"s_cbranch_execnz" , (ins SOPPBrTarget:$simm16),
12311231
"$simm16"
12321232
>;
12331233
} // End Uses = [EXEC]
12341234

12351235
defm S_CBRANCH_CDBGSYS : SOPP_With_Relaxation <
1236-
"s_cbranch_cdbgsys" , (ins sopp_brtarget:$simm16),
1236+
"s_cbranch_cdbgsys" , (ins SOPPBrTarget:$simm16),
12371237
"$simm16"
12381238
>;
12391239

12401240
defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_With_Relaxation <
1241-
"s_cbranch_cdbgsys_and_user" , (ins sopp_brtarget:$simm16),
1241+
"s_cbranch_cdbgsys_and_user" , (ins SOPPBrTarget:$simm16),
12421242
"$simm16"
12431243
>;
12441244

12451245
defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_With_Relaxation <
1246-
"s_cbranch_cdbgsys_or_user" , (ins sopp_brtarget:$simm16),
1246+
"s_cbranch_cdbgsys_or_user" , (ins SOPPBrTarget:$simm16),
12471247
"$simm16"
12481248
>;
12491249

12501250
defm S_CBRANCH_CDBGUSER : SOPP_With_Relaxation <
1251-
"s_cbranch_cdbguser" , (ins sopp_brtarget:$simm16),
1251+
"s_cbranch_cdbguser" , (ins SOPPBrTarget:$simm16),
12521252
"$simm16"
12531253
>;
12541254

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