Skip to content

Commit c35ca3a

Browse files
amy-kwanamy-kwan
committed
[PowerPC] Implement XL compat __fnabs and __fnabss builtins.
This patch implements the following floating point negative absolute value builtins that required for compatibility with the XL compiler: ``` double __fnabs(double); float __fnabss(float); ``` These builtins will emit : - fnabs on PWR6 and below, or if VSX is disabled. - xsnabsdp on PWR7 and above, if VSX is enabled. Differential Revision: https://reviews.llvm.org/D125506
1 parent 559b8fc commit c35ca3a

File tree

10 files changed

+123
-1
lines changed

10 files changed

+123
-1
lines changed

‎clang/include/clang/Basic/BuiltinsPPC.def

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,9 @@ BUILTIN(__builtin_ppc_maxfs, "ffff.", "t")
159159
BUILTIN(__builtin_ppc_minfe, "LdLdLdLd.", "t")
160160
BUILTIN(__builtin_ppc_minfl, "dddd.", "t")
161161
BUILTIN(__builtin_ppc_minfs, "ffff.", "t")
162+
// Floating Negative Absolute Value
163+
BUILTIN(__builtin_ppc_fnabs, "dd", "")
164+
BUILTIN(__builtin_ppc_fnabss, "ff", "")
162165

163166
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
164167

‎clang/lib/Basic/Targets/PPC.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -252,6 +252,8 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
252252
Builder.defineMacro("__test_data_class", "__builtin_ppc_test_data_class");
253253
Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv");
254254
Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs");
255+
Builder.defineMacro("__fnabs", "__builtin_ppc_fnabs");
256+
Builder.defineMacro("__fnabss", "__builtin_ppc_fnabss");
255257
Builder.defineMacro("__builtin_maxfe", "__builtin_ppc_maxfe");
256258
Builder.defineMacro("__builtin_maxfl", "__builtin_ppc_maxfl");
257259
Builder.defineMacro("__builtin_maxfs", "__builtin_ppc_maxfs");

‎clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
// REQUIRES: powerpc-registered-target
2+
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
3+
// RUN: -emit-llvm %s -target-cpu pwr8 -o - | FileCheck %s
4+
// RUN: %clang_cc1 -triple powerpc-unknown-aix \
5+
// RUN: -emit-llvm %s -target-cpu pwr8 -o - | FileCheck %s
6+
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
7+
// RUN: -emit-llvm %s -target-cpu pwr7 -o - | FileCheck %s
8+
// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
9+
// RUN: -emit-llvm %s -target-cpu pwr7 -o - | FileCheck %s
10+
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
11+
// RUN: -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s
12+
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
13+
// RUN: -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s
14+
// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
15+
// RUN: -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s
16+
// RUN: %clang_cc1 -triple powerpc-unknown-aix \
17+
// RUN: -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s
18+
19+
extern float f;
20+
extern double d;
21+
22+
// CHECK-LABEL: @test_fnabs(
23+
// CHECK: [[TMP0:%.*]] = load double, ptr @d
24+
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.ppc.fnabs(double [[TMP0]])
25+
// CHECK-NEXT: ret double [[TMP1]]
26+
double test_fnabs() {
27+
return __fnabs (d);
28+
}
29+
30+
// CHECK-LABEL: @test_fnabss(
31+
// CHECK: [[TMP0:%.*]] = load float, ptr @f
32+
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ppc.fnabss(float [[TMP0]])
33+
// CHECK-NEXT: ret float [[TMP1]]
34+
float test_fnabss() {
35+
return __fnabss (f);
36+
}

‎llvm/include/llvm/IR/IntrinsicsPowerPC.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1801,6 +1801,12 @@ let TargetPrefix = "ppc" in {
18011801
def int_ppc_test_data_class_f : Intrinsic<[llvm_i32_ty],
18021802
[llvm_float_ty, llvm_i32_ty],
18031803
[IntrNoMem, ImmArg<ArgIndex<1>>]>;
1804+
def int_ppc_fnabs
1805+
: GCCBuiltin<"__builtin_ppc_fnabs">,
1806+
Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
1807+
def int_ppc_fnabss
1808+
: GCCBuiltin<"__builtin_ppc_fnabss">,
1809+
Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
18041810

18051811
def int_ppc_convert_f128_to_ppcf128
18061812
: Intrinsic<[llvm_ppcf128_ty], [llvm_f128_ty], [IntrNoMem]>;

‎llvm/lib/Target/PowerPC/P10InstrResources.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -956,7 +956,7 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read],
956956
WAIT,
957957
XSABSDP,
958958
XSABSQP,
959-
XSNABSDP,
959+
XSNABSDP, XSNABSDPs,
960960
XSNABSQP,
961961
XSNEGDP,
962962
XSNEGQP,

‎llvm/lib/Target/PowerPC/P9InstrResources.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
156156
MCRF,
157157
MCRXRX,
158158
XSNABSDP,
159+
XSNABSDPs,
159160
XSXEXPDP,
160161
XSABSDP,
161162
XSNEGDP,

‎llvm/lib/Target/PowerPC/PPCBack2BackFusion.def

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -434,6 +434,7 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
434434
XSMINDP,
435435
XSMINJDP,
436436
XSNABSDP,
437+
XSNABSDPs,
437438
XSNABSQP,
438439
XSNEGDP,
439440
XSNEGQP,
@@ -978,6 +979,7 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
978979
XSMINDP,
979980
XSMINJDP,
980981
XSNABSDP,
982+
XSNABSDPs,
981983
XSNABSQP,
982984
XSNEGDP,
983985
XSNEGQP,

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3240,6 +3240,8 @@ def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>;
32403240
def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>;
32413241
def : Pat<(int_ppc_fre f64:$A), (FRE $A)>;
32423242
def : Pat<(int_ppc_fres f32:$A), (FRES $A)>;
3243+
def : Pat<(int_ppc_fnabs f64:$A), (FNABSD $A)>;
3244+
def : Pat<(int_ppc_fnabss f32:$A), (FNABSS $A)>;
32433245

32443246
include "PPCInstrAltivec.td"
32453247
include "PPCInstrSPE.td"

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -703,6 +703,11 @@ let hasSideEffects = 0 in {
703703
(outs vsfrc:$XT), (ins vsfrc:$XB),
704704
"xsnabsdp $XT, $XB", IIC_VecFP,
705705
[(set f64:$XT, (fneg (fabs f64:$XB)))]>;
706+
let isCodeGenOnly = 1 in
707+
def XSNABSDPs : XX2Form<60, 361,
708+
(outs vssrc:$XT), (ins vssrc:$XB),
709+
"xsnabsdp $XT, $XB", IIC_VecFP,
710+
[(set f32:$XT, (fneg (fabs f32:$XB)))]>;
706711
def XSNEGDP : XX2Form<60, 377,
707712
(outs vsfrc:$XT), (ins vsfrc:$XB),
708713
"xsnegdp $XT, $XB", IIC_VecFP,
@@ -2871,6 +2876,8 @@ def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (XSMSUBMDP $A, $B, $C)>;
28712876
def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
28722877
def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
28732878
def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
2879+
def : Pat<(int_ppc_fnabs f64:$A), (XSNABSDP $A)>;
2880+
def : Pat<(int_ppc_fnabss f32:$A), (XSNABSDPs $A)>;
28742881

28752882
// XXMRG[LH]W is a direct replacement for VMRG[LH]W respectively.
28762883
// Prefer the VSX form for greater register range.

‎llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \
4+
; RUN: FileCheck %s --check-prefix=CHECK-DEFAULT
5+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
6+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
7+
; RUN: --check-prefix=CHECK-DEFAULT
8+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
9+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
10+
; RUN: --check-prefix=CHECK-DEFAULT
11+
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr7 \
12+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
13+
; RUN: --check-prefix=CHECK-DEFAULT
14+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr6 \
15+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mattr=+vsx < %s | \
16+
; RUN: FileCheck %s --check-prefix=CHECK-DEFAULT
17+
18+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
19+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
20+
; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
21+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
22+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
23+
; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
24+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
25+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
26+
; RUN: -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
27+
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
28+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
29+
; RUN: -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
30+
31+
declare double @llvm.ppc.fnabs(double)
32+
declare float @llvm.ppc.fnabss(float)
33+
34+
define double @test_fnabs2(double %d) {
35+
; CHECK-DEFAULT-LABEL: test_fnabs2:
36+
; CHECK-DEFAULT: # %bb.0: # %entry
37+
; CHECK-DEFAULT-NEXT: xsnabsdp f1, f1
38+
; CHECK-DEFAULT-NEXT: blr
39+
;
40+
; CHECK-NOVSX-LABEL: test_fnabs2:
41+
; CHECK-NOVSX: # %bb.0: # %entry
42+
; CHECK-NOVSX-NEXT: fnabs f1, f1
43+
; CHECK-NOVSX-NEXT: blr
44+
entry:
45+
%0 = tail call double @llvm.ppc.fnabs(double %d)
46+
ret double %0
47+
}
48+
49+
define float @test_fnabss(float %f) {
50+
; CHECK-DEFAULT-LABEL: test_fnabss:
51+
; CHECK-DEFAULT: # %bb.0: # %entry
52+
; CHECK-DEFAULT-NEXT: xsnabsdp f1, f1
53+
; CHECK-DEFAULT-NEXT: blr
54+
;
55+
; CHECK-NOVSX-LABEL: test_fnabss:
56+
; CHECK-NOVSX: # %bb.0: # %entry
57+
; CHECK-NOVSX-NEXT: fnabs f1, f1
58+
; CHECK-NOVSX-NEXT: blr
59+
entry:
60+
%0 = tail call float @llvm.ppc.fnabss(float %f)
61+
ret float %0
62+
}
63+

0 commit comments

Comments
 (0)