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[AMDGPU][AsmParser][NFC] Refine defining single-bit custom operands.
Reviewed By: dp Differential Revision: https://reviews.llvm.org/D141301
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 13 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -381,7 +381,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
381381
bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }
382382
bool isBankMask() const { return isImmTy(ImmTyDppBankMask); }
383383
bool isRowMask() const { return isImmTy(ImmTyDppRowMask); }
384-
bool isBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }
384+
bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }
385385
bool isFI() const { return isImmTy(ImmTyDppFi); }
386386
bool isSDWADstSel() const { return isImmTy(ImmTySdwaDstSel); }
387387
bool isSDWASrc0Sel() const { return isImmTy(ImmTySdwaSrc0Sel); }
@@ -1579,6 +1579,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
15791579
OperandMatchResultTy parseSymbolicOrNumericFormat(int64_t &Format);
15801580
OperandMatchResultTy parseNumericFormat(int64_t &Format);
15811581
OperandMatchResultTy parseFlatOffset(OperandVector &Operands);
1582+
OperandMatchResultTy parseR128A16(OperandVector &Operands);
15821583
bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val);
15831584
bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc);
15841585

@@ -1779,7 +1780,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17791780
int64_t parseDPPCtrlPerm();
17801781
AMDGPUOperand::Ptr defaultRowMask() const;
17811782
AMDGPUOperand::Ptr defaultBankMask() const;
1782-
AMDGPUOperand::Ptr defaultBoundCtrl() const;
1783+
AMDGPUOperand::Ptr defaultDppBoundCtrl() const;
17831784
AMDGPUOperand::Ptr defaultFI() const;
17841785
void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
17851786
void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {
@@ -6370,6 +6371,14 @@ OperandMatchResultTy AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {
63706371
return Res;
63716372
}
63726373

6374+
OperandMatchResultTy AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {
6375+
OperandMatchResultTy Res =
6376+
parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16);
6377+
if (Res == MatchOperand_NoMatch)
6378+
Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);
6379+
return Res;
6380+
}
6381+
63736382
//===----------------------------------------------------------------------===//
63746383
// ds
63756384
//===----------------------------------------------------------------------===//
@@ -7992,7 +8001,7 @@ static bool ConvertOmodDiv(int64_t &Div) {
79928001
// Both bound_ctrl:0 and bound_ctrl:1 are encoded as 1.
79938002
// This is intentional and ensures compatibility with sp3.
79948003
// See bug 35397 for details.
7995-
static bool ConvertBoundCtrl(int64_t &BoundCtrl) {
8004+
static bool ConvertDppBoundCtrl(int64_t &BoundCtrl) {
79968005
if (BoundCtrl == 0 || BoundCtrl == 1) {
79978006
BoundCtrl = 1;
79988007
return true;
@@ -8683,7 +8692,7 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBankMask() const {
86838692
return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppBankMask);
86848693
}
86858694

8686-
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBoundCtrl() const {
8695+
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppBoundCtrl() const {
86878696
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppBoundCtrl);
86888697
}
86898698

@@ -9104,35 +9113,14 @@ AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) {
91049113
}
91059114
return Res;
91069115
}
9107-
case MCK_ImmBoundCtrl:
9108-
return parseIntWithPrefix("bound_ctrl", Operands,
9109-
AMDGPUOperand::ImmTyDppBoundCtrl,
9110-
ConvertBoundCtrl);
91119116
case MCK_ImmCBSZ:
91129117
return parseIntWithPrefix("cbsz", Operands, AMDGPUOperand::ImmTyCBSZ);
9113-
case MCK_ImmClampSI:
9114-
return parseNamedBit("clamp", Operands, AMDGPUOperand::ImmTyClampSI);
91159118
case MCK_ImmCPol:
91169119
return parseCPol(Operands);
9117-
case MCK_ImmD16:
9118-
return parseNamedBit("d16", Operands, AMDGPUOperand::ImmTyD16);
9119-
case MCK_ImmDA:
9120-
return parseNamedBit("da", Operands, AMDGPUOperand::ImmTyDA);
9121-
case MCK_ImmExpCompr:
9122-
return parseNamedBit("compr", Operands, AMDGPUOperand::ImmTyExpCompr);
9123-
case MCK_ImmExpVM:
9124-
return parseNamedBit("vm", Operands, AMDGPUOperand::ImmTyExpVM);
91259120
case MCK_ImmFI:
91269121
return parseIntWithPrefix("fi", Operands, AMDGPUOperand::ImmTyDppFi);
91279122
case MCK_gds:
9128-
case MCK_ImmGDS:
91299123
return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);
9130-
case MCK_ImmA16:
9131-
return parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);
9132-
case MCK_ImmHigh:
9133-
return parseNamedBit("high", Operands, AMDGPUOperand::ImmTyHigh);
9134-
case MCK_ImmLWE:
9135-
return parseNamedBit("lwe", Operands, AMDGPUOperand::ImmTyLWE);
91369124
case MCK_ImmNegHi:
91379125
return parseOperandArrayWithPrefix("neg_hi", Operands,
91389126
AMDGPUOperand::ImmTyNegHi);
@@ -9149,13 +9137,6 @@ AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) {
91499137
case MCK_ImmOpSelHi:
91509138
return parseOperandArrayWithPrefix("op_sel_hi", Operands,
91519139
AMDGPUOperand::ImmTyOpSelHi);
9152-
case MCK_ImmR128A16: {
9153-
OperandMatchResultTy Res =
9154-
parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16);
9155-
if (Res == MatchOperand_NoMatch)
9156-
Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);
9157-
return Res;
9158-
}
91599140
case MCK_ImmRowMask:
91609141
return parseIntWithPrefix("row_mask", Operands,
91619142
AMDGPUOperand::ImmTyDppRowMask);
@@ -9167,13 +9148,8 @@ AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) {
91679148
return parseSDWASel(Operands, "src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel);
91689149
case MCK_ImmSDWASrc1Sel:
91699150
return parseSDWASel(Operands, "src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel);
9170-
case MCK_ImmSWZ:
9171-
return parseNamedBit("swz", Operands, AMDGPUOperand::ImmTySWZ);
91729151
case MCK_tfe:
9173-
case MCK_ImmTFE:
91749152
return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);
9175-
case MCK_ImmUNorm:
9176-
return parseNamedBit("unorm", Operands, AMDGPUOperand::ImmTyUNorm);
91779153
}
91789154
return tryCustomParseOperand(Operands, MCK);
91799155
}
@@ -9199,7 +9175,6 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
91999175
case MCK_offen:
92009176
return Operand.isOffen() ? Match_Success : Match_InvalidOperand;
92019177
case MCK_tfe:
9202-
case MCK_ImmTFE:
92039178
return Operand.isTFE() ? Match_Success : Match_InvalidOperand;
92049179
case MCK_SSrcB32:
92059180
// When operands have expression values, they will return true for isToken,

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1026,9 +1026,9 @@ void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
10261026
printU4ImmOperand(MI, OpNo, STI, O);
10271027
}
10281028

1029-
void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
1030-
const MCSubtargetInfo &STI,
1031-
raw_ostream &O) {
1029+
void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
1030+
const MCSubtargetInfo &STI,
1031+
raw_ostream &O) {
10321032
unsigned Imm = MI->getOperand(OpNo).getImm();
10331033
if (Imm) {
10341034
O << " bound_ctrl:1";

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -136,8 +136,8 @@ class AMDGPUInstPrinter : public MCInstPrinter {
136136
raw_ostream &O);
137137
void printBankMask(const MCInst *MI, unsigned OpNo,
138138
const MCSubtargetInfo &STI, raw_ostream &O);
139-
void printBoundCtrl(const MCInst *MI, unsigned OpNo,
140-
const MCSubtargetInfo &STI, raw_ostream &O);
139+
void printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
140+
const MCSubtargetInfo &STI, raw_ostream &O);
141141
void printFI(const MCInst *MI, unsigned OpNo,
142142
const MCSubtargetInfo &STI, raw_ostream &O);
143143
void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 43 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1157,23 +1157,6 @@ class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
11571157
let DefaultMethod = !if(Optional, "default"#CName, ?);
11581158
}
11591159

1160-
class NamedOperandBit<string Name, AsmOperandClass MatchClass> : Operand<i1> {
1161-
let PrintMethod = "print"#Name;
1162-
let ParserMatchClass = MatchClass;
1163-
}
1164-
1165-
class NamedOperandBit_0<string Name, AsmOperandClass MatchClass> :
1166-
OperandWithDefaultOps<i1, (ops (i1 0))> {
1167-
let PrintMethod = "print"#Name;
1168-
let ParserMatchClass = MatchClass;
1169-
}
1170-
1171-
class NamedOperandBit_1<string Name, AsmOperandClass MatchClass> :
1172-
OperandWithDefaultOps<i1, (ops (i1 1))> {
1173-
let PrintMethod = "print"#Name;
1174-
let ParserMatchClass = MatchClass;
1175-
}
1176-
11771160
class CustomOperandClass<string CName, bit Optional> : AsmOperandClass {
11781161
let Name = CName;
11791162
let PredicateMethod = "is"#CName;
@@ -1183,23 +1166,43 @@ class CustomOperandClass<string CName, bit Optional> : AsmOperandClass {
11831166
let DefaultMethod = "default"#CName;
11841167
}
11851168

1169+
class CustomOperandProps<bit Optional = 0, string Name = NAME,
1170+
AsmOperandClass Class = CustomOperandClass<Name, Optional>> {
1171+
string PrintMethod = "print"#Name;
1172+
AsmOperandClass ParserMatchClass = Class;
1173+
}
1174+
11861175
class CustomOperand<ValueType Type, bit Optional = 0, string Name = NAME,
11871176
AsmOperandClass Class = CustomOperandClass<Name, Optional>>
1188-
: Operand<Type> {
1189-
let PrintMethod = "print"#Name;
1190-
let ParserMatchClass = Class;
1177+
: Operand<Type>, CustomOperandProps<Optional, Name, Class>;
1178+
1179+
class NamedIntOperandClass<string Prefix, string Name, string ConvertMethod>
1180+
: CustomOperandClass<Name, 1> {
1181+
string ImmTy = "AMDGPUOperand::ImmTy"#Name;
1182+
let ParserMethod =
1183+
"[this](OperandVector &Operands) -> OperandMatchResultTy { "#
1184+
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#ImmTy#", "#
1185+
ConvertMethod#"); }";
11911186
}
11921187

1193-
class NamedIntOperandClass<string Prefix, string Name>
1188+
class NamedIntOperand<ValueType Type, string Prefix, string Name = NAME,
1189+
string ConvertMethod = "nullptr">
1190+
: CustomOperand<Type, 1, Name, NamedIntOperandClass<Prefix, Name, ConvertMethod>>;
1191+
1192+
class BitOperandClass<string Id, string Name>
11941193
: CustomOperandClass<Name, 1> {
11951194
string ImmTy = "AMDGPUOperand::ImmTy"#Name;
11961195
let ParserMethod =
11971196
"[this](OperandVector &Operands) -> OperandMatchResultTy { "#
1198-
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#ImmTy#"); }";
1197+
"return parseNamedBit(\""#Id#"\", Operands, "#ImmTy#"); }";
11991198
}
12001199

1201-
class NamedIntOperand<ValueType Type, string Prefix, string Name = NAME>
1202-
: CustomOperand<Type, 1, Name, NamedIntOperandClass<Prefix, Name>>;
1200+
class NamedBitOperand<string Id, string Name = NAME>
1201+
: CustomOperand<i1, 1, Name, BitOperandClass<Id, Name>>;
1202+
1203+
class DefaultOperand_0<CustomOperand Op>
1204+
: OperandWithDefaultOps<Op.Type, (ops (Op.Type 0))>,
1205+
CustomOperandProps<1, Op.ParserMatchClass.Name, Op.ParserMatchClass>;
12031206

12041207
class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
12051208
let PrintMethod = "print"#Name;
@@ -1231,33 +1234,33 @@ def offset : NamedIntOperand<i16, "offset", "Offset">;
12311234
def offset0 : NamedIntOperand<i8, "offset0", "Offset0">;
12321235
def offset1 : NamedIntOperand<i8, "offset1", "Offset1">;
12331236

1234-
def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
1237+
def gds : NamedBitOperand<"gds", "GDS">;
12351238

12361239
def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
12371240
def omod0 : NamedOperandU32_0<"OModSI", NamedMatchClass<"OModSI">>;
12381241

12391242
// We need to make the cases with a default of 0 distinct from no
12401243
// default to help deal with some cases where the operand appears
12411244
// before a mandatory operand.
1242-
def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
1243-
def clampmod0 : NamedOperandBit_0<"ClampSI", NamedMatchClass<"ClampSI">>;
1244-
def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
1245+
def clampmod : NamedBitOperand<"clamp", "ClampSI">;
1246+
def clampmod0 : DefaultOperand_0<clampmod>;
1247+
def highmod : NamedBitOperand<"high", "High">;
12451248

12461249
def CPol : NamedOperandU32<"CPol", NamedMatchClass<"CPol">>;
12471250
def CPol_0 : NamedOperandU32Default0<"CPol", NamedMatchClass<"CPol">>;
12481251
def CPol_GLC1 : NamedOperandU32Default1<"CPol", NamedMatchClass<"CPol">>;
12491252

1250-
def TFE : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
1251-
def SWZ : NamedOperandBit<"SWZ", NamedMatchClass<"SWZ">>;
1252-
def SWZ_0 : NamedOperandBit_0<"SWZ", NamedMatchClass<"SWZ">>;
1253-
def UNorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
1254-
def DA : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
1255-
def R128A16 : NamedOperandBit<"R128A16", NamedMatchClass<"R128A16">>;
1256-
def A16 : NamedOperandBit<"A16", NamedMatchClass<"A16">>;
1257-
def D16 : NamedOperandBit<"D16", NamedMatchClass<"D16">>;
1258-
def LWE : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
1259-
def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>;
1260-
def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>;
1253+
def TFE : NamedBitOperand<"tfe">;
1254+
def SWZ : NamedBitOperand<"swz">;
1255+
def SWZ_0 : DefaultOperand_0<SWZ>;
1256+
def UNorm : NamedBitOperand<"unorm">;
1257+
def DA : NamedBitOperand<"da">;
1258+
def R128A16 : CustomOperand<i1, 1>;
1259+
def A16 : NamedBitOperand<"a16">;
1260+
def D16 : NamedBitOperand<"d16">;
1261+
def LWE : NamedBitOperand<"lwe">;
1262+
def exp_compr : NamedBitOperand<"compr", "ExpCompr">;
1263+
def exp_vm : NamedBitOperand<"vm", "ExpVM">;
12611264

12621265
def FORMAT : CustomOperand<i8>;
12631266

@@ -1279,7 +1282,7 @@ def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
12791282

12801283
def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>;
12811284
def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>;
1282-
def bound_ctrl : NamedOperandBit<"BoundCtrl", NamedMatchClass<"BoundCtrl">>;
1285+
def bound_ctrl : NamedIntOperand<i1, "bound_ctrl", "DppBoundCtrl", "ConvertDppBoundCtrl">;
12831286
def FI : NamedOperandU32<"FI", NamedMatchClass<"FI">>;
12841287

12851288
def blgp : NamedOperandU32<"BLGP", NamedMatchClass<"BLGP">>;

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