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XinWang10XinWang10
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[X86][MC] Fix wrong encoding of promoted BMI instructions due to missing NoCD8 (#78386)
Address review comments in #76709 Add `NoCD8` to class `ITy`, and rewrite the promoted instructions with `ITy` to avoid unexpected incorrect encoding about `NoCD8`.
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‎llvm/lib/Target/X86/X86InstrMisc.td

+18-27
Original file line numberDiff line numberDiff line change
@@ -1375,39 +1375,30 @@ let Predicates = [HasBMI2, NoTBM, HasEGPR] in {
13751375
(MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
13761376
}
13771377

1378-
multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1379-
X86MemOperand x86memop, SDPatternOperator OpNode,
1380-
PatFrag ld_frag, string Suffix = ""> {
1381-
def rr#Suffix : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1382-
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1383-
[(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>,
1384-
NoCD8, VVVV, Sched<[WriteALU]>;
1385-
def rm#Suffix : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1386-
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1387-
[(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>,
1388-
NoCD8, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
1378+
multiclass PdepPext<string m, X86TypeInfo t, SDPatternOperator node,
1379+
string suffix = ""> {
1380+
def rr#suffix : ITy<0xF5, MRMSrcReg, t, (outs t.RegClass:$dst),
1381+
(ins t.RegClass:$src1, t.RegClass:$src2), m, binop_ndd_args,
1382+
[(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2))]>,
1383+
T8, VVVV, Sched<[WriteALU]>;
1384+
def rm#suffix : ITy<0xF5, MRMSrcMem, t, (outs t.RegClass:$dst),
1385+
(ins t.RegClass:$src1, t.MemOperand:$src2), m, binop_ndd_args,
1386+
[(set t.RegClass:$dst, (node t.RegClass:$src1, (t.LoadNode addr:$src2)))]>,
1387+
T8, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
13891388
}
13901389

13911390
let Predicates = [HasBMI2, NoEGPR] in {
1392-
defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1393-
X86pdep, loadi32>, T8, XD, VEX;
1394-
defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1395-
X86pdep, loadi64>, T8, XD, REX_W, VEX;
1396-
defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1397-
X86pext, loadi32>, T8, XS, VEX;
1398-
defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1399-
X86pext, loadi64>, T8, XS, REX_W, VEX;
1391+
defm PDEP32 : PdepPext<"pdep", Xi32, X86pdep>, XD, VEX;
1392+
defm PDEP64 : PdepPext<"pdep", Xi64, X86pdep>, XD, REX_W, VEX;
1393+
defm PEXT32 : PdepPext<"pext", Xi32, X86pext>, XS, VEX;
1394+
defm PEXT64 : PdepPext<"pext", Xi64, X86pext>, XS, REX_W, VEX;
14001395
}
14011396

14021397
let Predicates = [HasBMI2, HasEGPR] in {
1403-
defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1404-
X86pdep, loadi32, "_EVEX">, T8, XD, EVEX;
1405-
defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1406-
X86pdep, loadi64, "_EVEX">, T8, XD, REX_W, EVEX;
1407-
defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1408-
X86pext, loadi32, "_EVEX">, T8, XS, EVEX;
1409-
defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1410-
X86pext, loadi64, "_EVEX">, T8, XS, REX_W, EVEX;
1398+
defm PDEP32 : PdepPext<"pdep", Xi32, X86pdep, "_EVEX">, XD, EVEX;
1399+
defm PDEP64 : PdepPext<"pdep", Xi64, X86pdep, "_EVEX">, XD, REX_W, EVEX;
1400+
defm PEXT32 : PdepPext<"pext", Xi32, X86pext, "_EVEX">, XS, EVEX;
1401+
defm PEXT64 : PdepPext<"pext", Xi64, X86pext, "_EVEX">, XS, REX_W, EVEX;
14111402
}
14121403

14131404
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/X86/X86InstrSSE.td

+2-2
Original file line numberDiff line numberDiff line change
@@ -6663,14 +6663,14 @@ let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
66636663
class Crc32r<X86TypeInfo t, RegisterClass rc, SDPatternOperator node>
66646664
: ITy<0xF1, MRMSrcReg, t, (outs rc:$dst), (ins rc:$src1, t.RegClass:$src2),
66656665
"crc32", binop_args, [(set rc:$dst, (node rc:$src1, t.RegClass:$src2))]>,
6666-
Sched<[WriteCRC32]>, NoCD8 {
6666+
Sched<[WriteCRC32]> {
66676667
let Constraints = "$src1 = $dst";
66686668
}
66696669

66706670
class Crc32m<X86TypeInfo t, RegisterClass rc, SDPatternOperator node>
66716671
: ITy<0xF1, MRMSrcMem, t, (outs rc:$dst), (ins rc:$src1, t.MemOperand:$src2),
66726672
"crc32", binop_args, [(set rc:$dst, (node rc:$src1, (load addr:$src2)))]>,
6673-
Sched<[WriteCRC32.Folded, WriteCRC32.ReadAfterFold]>, NoCD8 {
6673+
Sched<[WriteCRC32.Folded, WriteCRC32.ReadAfterFold]> {
66746674
let Constraints = "$src1 = $dst";
66756675
}
66766676

‎llvm/lib/Target/X86/X86InstrUtils.td

+3-3
Original file line numberDiff line numberDiff line change
@@ -113,9 +113,9 @@ class NDD<bit ndd, Map map = OB> {
113113
Map OpMap = !if(!eq(ndd, 0), map, T_MAP4);
114114
}
115115
// NF - Helper for NF (no flags update) instructions
116-
class NF: T_MAP4, EVEX, EVEX_NF, NoCD8;
116+
class NF: T_MAP4, EVEX, EVEX_NF;
117117
// PL - Helper for promoted legacy instructions
118-
class PL: T_MAP4, EVEX, NoCD8, ExplicitEVEXPrefix;
118+
class PL: T_MAP4, EVEX, ExplicitEVEXPrefix;
119119

120120
//===----------------------------------------------------------------------===//
121121
// X86 Type infomation definitions
@@ -961,7 +961,7 @@ class ITy<bits<8> o, Format f, X86TypeInfo t, dag outs, dag ins, string m,
961961
string args, list<dag> p>
962962
: I<{o{7}, o{6}, o{5}, o{4}, o{3}, o{2}, o{1},
963963
!if(!eq(t.HasEvenOpcode, 1), 0, o{0})}, f, outs, ins,
964-
!strconcat(m, "{", t.InstrSuffix, "}\t", args), p> {
964+
!strconcat(m, "{", t.InstrSuffix, "}\t", args), p>, NoCD8 {
965965
let hasSideEffects = 0;
966966
let hasREX_W = t.HasREX_W;
967967
}

‎llvm/test/MC/Disassembler/X86/apx/bmi2.txt

+10-10
Original file line numberDiff line numberDiff line change
@@ -13,11 +13,11 @@
1313

1414
# ATT: mulxl 123(%rax,%rbx,4), %ecx, %edx
1515
# INTEL: mulx edx, ecx, dword ptr [rax + 4*rbx + 123]
16-
0x62,0xf2,0x77,0x08,0xf6,0x94,0x98,0x7b,0x00,0x00,0x00
16+
0x62,0xf2,0x77,0x08,0xf6,0x54,0x98,0x7b
1717

1818
# ATT: mulxq 123(%rax,%rbx,4), %r9, %r15
1919
# INTEL: mulx r15, r9, qword ptr [rax + 4*rbx + 123]
20-
0x62,0x72,0xb7,0x08,0xf6,0xbc,0x98,0x7b,0x00,0x00,0x00
20+
0x62,0x72,0xb7,0x08,0xf6,0x7c,0x98,0x7b
2121

2222
# ATT: mulxl %r18d, %r22d, %r26d
2323
# INTEL: mulx r26d, r22d, r18d
@@ -115,11 +115,11 @@
115115

116116
# ATT: rorxl $123, 123(%rax,%rbx,4), %ecx
117117
# INTEL: rorx ecx, dword ptr [rax + 4*rbx + 123], 123
118-
0x62,0xf3,0x7f,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b
118+
0x62,0xf3,0x7f,0x08,0xf0,0x4c,0x98,0x7b,0x7b
119119

120120
# ATT: rorxq $123, 123(%rax,%rbx,4), %r9
121121
# INTEL: rorx r9, qword ptr [rax + 4*rbx + 123], 123
122-
0x62,0x73,0xff,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b
122+
0x62,0x73,0xff,0x08,0xf0,0x4c,0x98,0x7b,0x7b
123123

124124
# ATT: rorxl $123, %r18d, %r22d
125125
# INTEL: rorx r22d, r18d, 123
@@ -145,15 +145,15 @@
145145

146146
# ATT: sarxl %ecx, 123(%rax,%rbx,4), %edx
147147
# INTEL: sarx edx, dword ptr [rax + 4*rbx + 123], ecx
148-
0x62,0xf2,0x76,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00
148+
0x62,0xf2,0x76,0x08,0xf7,0x54,0x98,0x7b
149149

150150
# ATT: sarxq %r9, %r15, %r11
151151
# INTEL: sarx r11, r15, r9
152152
0x62,0x52,0xb6,0x08,0xf7,0xdf
153153

154154
# ATT: sarxq %r9, 123(%rax,%rbx,4), %r15
155155
# INTEL: sarx r15, qword ptr [rax + 4*rbx + 123], r9
156-
0x62,0x72,0xb6,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00
156+
0x62,0x72,0xb6,0x08,0xf7,0x7c,0x98,0x7b
157157

158158
# ATT: sarxl %r18d, %r22d, %r26d
159159
# INTEL: sarx r26d, r22d, r18d
@@ -179,15 +179,15 @@
179179

180180
# ATT: shlxl %ecx, 123(%rax,%rbx,4), %edx
181181
# INTEL: shlx edx, dword ptr [rax + 4*rbx + 123], ecx
182-
0x62,0xf2,0x75,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00
182+
0x62,0xf2,0x75,0x08,0xf7,0x54,0x98,0x7b
183183

184184
# ATT: shlxq %r9, %r15, %r11
185185
# INTEL: shlx r11, r15, r9
186186
0x62,0x52,0xb5,0x08,0xf7,0xdf
187187

188188
# ATT: shlxq %r9, 123(%rax,%rbx,4), %r15
189189
# INTEL: shlx r15, qword ptr [rax + 4*rbx + 123], r9
190-
0x62,0x72,0xb5,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00
190+
0x62,0x72,0xb5,0x08,0xf7,0x7c,0x98,0x7b
191191

192192
# ATT: shlxl %r18d, %r22d, %r26d
193193
# INTEL: shlx r26d, r22d, r18d
@@ -213,15 +213,15 @@
213213

214214
# ATT: shrxl %ecx, 123(%rax,%rbx,4), %edx
215215
# INTEL: shrx edx, dword ptr [rax + 4*rbx + 123], ecx
216-
0x62,0xf2,0x77,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00
216+
0x62,0xf2,0x77,0x08,0xf7,0x54,0x98,0x7b
217217

218218
# ATT: shrxq %r9, %r15, %r11
219219
# INTEL: shrx r11, r15, r9
220220
0x62,0x52,0xb7,0x08,0xf7,0xdf
221221

222222
# ATT: shrxq %r9, 123(%rax,%rbx,4), %r15
223223
# INTEL: shrx r15, qword ptr [rax + 4*rbx + 123], r9
224-
0x62,0x72,0xb7,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00
224+
0x62,0x72,0xb7,0x08,0xf7,0x7c,0x98,0x7b
225225

226226
# ATT: shrxl %r18d, %r22d, %r26d
227227
# INTEL: shrx r26d, r22d, r18d

‎llvm/test/MC/X86/apx/bmi2-att.s

+10-10
Original file line numberDiff line numberDiff line change
@@ -15,11 +15,11 @@
1515
{evex} mulxq %r9, %r15, %r11
1616

1717
# CHECK: {evex} mulxl 123(%rax,%rbx,4), %ecx, %edx
18-
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf6,0x94,0x98,0x7b,0x00,0x00,0x00]
18+
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf6,0x54,0x98,0x7b]
1919
{evex} mulxl 123(%rax,%rbx,4), %ecx, %edx
2020

2121
# CHECK: {evex} mulxq 123(%rax,%rbx,4), %r9, %r15
22-
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf6,0xbc,0x98,0x7b,0x00,0x00,0x00]
22+
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf6,0x7c,0x98,0x7b]
2323
{evex} mulxq 123(%rax,%rbx,4), %r9, %r15
2424

2525
# CHECK: mulxl %r18d, %r22d, %r26d
@@ -117,11 +117,11 @@
117117
{evex} rorxq $123, %r9, %r15
118118

119119
# CHECK: {evex} rorxl $123, 123(%rax,%rbx,4), %ecx
120-
# CHECK: encoding: [0x62,0xf3,0x7f,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b]
120+
# CHECK: encoding: [0x62,0xf3,0x7f,0x08,0xf0,0x4c,0x98,0x7b,0x7b]
121121
{evex} rorxl $123, 123(%rax,%rbx,4), %ecx
122122

123123
# CHECK: {evex} rorxq $123, 123(%rax,%rbx,4), %r9
124-
# CHECK: encoding: [0x62,0x73,0xff,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b]
124+
# CHECK: encoding: [0x62,0x73,0xff,0x08,0xf0,0x4c,0x98,0x7b,0x7b]
125125
{evex} rorxq $123, 123(%rax,%rbx,4), %r9
126126

127127
# CHECK: rorxl $123, %r18d, %r22d
@@ -147,15 +147,15 @@
147147
{evex} sarxl %ecx, %edx, %r10d
148148

149149
# CHECK: {evex} sarxl %ecx, 123(%rax,%rbx,4), %edx
150-
# CHECK: encoding: [0x62,0xf2,0x76,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
150+
# CHECK: encoding: [0x62,0xf2,0x76,0x08,0xf7,0x54,0x98,0x7b]
151151
{evex} sarxl %ecx, 123(%rax,%rbx,4), %edx
152152

153153
# CHECK: {evex} sarxq %r9, %r15, %r11
154154
# CHECK: encoding: [0x62,0x52,0xb6,0x08,0xf7,0xdf]
155155
{evex} sarxq %r9, %r15, %r11
156156

157157
# CHECK: {evex} sarxq %r9, 123(%rax,%rbx,4), %r15
158-
# CHECK: encoding: [0x62,0x72,0xb6,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
158+
# CHECK: encoding: [0x62,0x72,0xb6,0x08,0xf7,0x7c,0x98,0x7b]
159159
{evex} sarxq %r9, 123(%rax,%rbx,4), %r15
160160

161161
# CHECK: sarxl %r18d, %r22d, %r26d
@@ -181,15 +181,15 @@
181181
{evex} shlxl %ecx, %edx, %r10d
182182

183183
# CHECK: {evex} shlxl %ecx, 123(%rax,%rbx,4), %edx
184-
# CHECK: encoding: [0x62,0xf2,0x75,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
184+
# CHECK: encoding: [0x62,0xf2,0x75,0x08,0xf7,0x54,0x98,0x7b]
185185
{evex} shlxl %ecx, 123(%rax,%rbx,4), %edx
186186

187187
# CHECK: {evex} shlxq %r9, %r15, %r11
188188
# CHECK: encoding: [0x62,0x52,0xb5,0x08,0xf7,0xdf]
189189
{evex} shlxq %r9, %r15, %r11
190190

191191
# CHECK: {evex} shlxq %r9, 123(%rax,%rbx,4), %r15
192-
# CHECK: encoding: [0x62,0x72,0xb5,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
192+
# CHECK: encoding: [0x62,0x72,0xb5,0x08,0xf7,0x7c,0x98,0x7b]
193193
{evex} shlxq %r9, 123(%rax,%rbx,4), %r15
194194

195195
# CHECK: shlxl %r18d, %r22d, %r26d
@@ -215,15 +215,15 @@
215215
{evex} shrxl %ecx, %edx, %r10d
216216

217217
# CHECK: {evex} shrxl %ecx, 123(%rax,%rbx,4), %edx
218-
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
218+
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf7,0x54,0x98,0x7b]
219219
{evex} shrxl %ecx, 123(%rax,%rbx,4), %edx
220220

221221
# CHECK: {evex} shrxq %r9, %r15, %r11
222222
# CHECK: encoding: [0x62,0x52,0xb7,0x08,0xf7,0xdf]
223223
{evex} shrxq %r9, %r15, %r11
224224

225225
# CHECK: {evex} shrxq %r9, 123(%rax,%rbx,4), %r15
226-
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
226+
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf7,0x7c,0x98,0x7b]
227227
{evex} shrxq %r9, 123(%rax,%rbx,4), %r15
228228

229229
# CHECK: shrxl %r18d, %r22d, %r26d

‎llvm/test/MC/X86/apx/bmi2-intel.s

+10-10
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,11 @@
1111
{evex} mulx r11, r15, r9
1212

1313
# CHECK: {evex} mulx edx, ecx, dword ptr [rax + 4*rbx + 123]
14-
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf6,0x94,0x98,0x7b,0x00,0x00,0x00]
14+
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf6,0x54,0x98,0x7b]
1515
{evex} mulx edx, ecx, dword ptr [rax + 4*rbx + 123]
1616

1717
# CHECK: {evex} mulx r15, r9, qword ptr [rax + 4*rbx + 123]
18-
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf6,0xbc,0x98,0x7b,0x00,0x00,0x00]
18+
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf6,0x7c,0x98,0x7b]
1919
{evex} mulx r15, r9, qword ptr [rax + 4*rbx + 123]
2020

2121
# CHECK: mulx r26d, r22d, r18d
@@ -113,11 +113,11 @@
113113
{evex} rorx r15, r9, 123
114114

115115
# CHECK: {evex} rorx ecx, dword ptr [rax + 4*rbx + 123], 123
116-
# CHECK: encoding: [0x62,0xf3,0x7f,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b]
116+
# CHECK: encoding: [0x62,0xf3,0x7f,0x08,0xf0,0x4c,0x98,0x7b,0x7b]
117117
{evex} rorx ecx, dword ptr [rax + 4*rbx + 123], 123
118118

119119
# CHECK: {evex} rorx r9, qword ptr [rax + 4*rbx + 123], 123
120-
# CHECK: encoding: [0x62,0x73,0xff,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b]
120+
# CHECK: encoding: [0x62,0x73,0xff,0x08,0xf0,0x4c,0x98,0x7b,0x7b]
121121
{evex} rorx r9, qword ptr [rax + 4*rbx + 123], 123
122122

123123
# CHECK: rorx r22d, r18d, 123
@@ -143,15 +143,15 @@
143143
{evex} sarx r10d, edx, ecx
144144

145145
# CHECK: {evex} sarx edx, dword ptr [rax + 4*rbx + 123], ecx
146-
# CHECK: encoding: [0x62,0xf2,0x76,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
146+
# CHECK: encoding: [0x62,0xf2,0x76,0x08,0xf7,0x54,0x98,0x7b]
147147
{evex} sarx edx, dword ptr [rax + 4*rbx + 123], ecx
148148

149149
# CHECK: {evex} sarx r11, r15, r9
150150
# CHECK: encoding: [0x62,0x52,0xb6,0x08,0xf7,0xdf]
151151
{evex} sarx r11, r15, r9
152152

153153
# CHECK: {evex} sarx r15, qword ptr [rax + 4*rbx + 123], r9
154-
# CHECK: encoding: [0x62,0x72,0xb6,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
154+
# CHECK: encoding: [0x62,0x72,0xb6,0x08,0xf7,0x7c,0x98,0x7b]
155155
{evex} sarx r15, qword ptr [rax + 4*rbx + 123], r9
156156

157157
# CHECK: sarx r26d, r22d, r18d
@@ -177,15 +177,15 @@
177177
{evex} shlx r10d, edx, ecx
178178

179179
# CHECK: {evex} shlx edx, dword ptr [rax + 4*rbx + 123], ecx
180-
# CHECK: encoding: [0x62,0xf2,0x75,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
180+
# CHECK: encoding: [0x62,0xf2,0x75,0x08,0xf7,0x54,0x98,0x7b]
181181
{evex} shlx edx, dword ptr [rax + 4*rbx + 123], ecx
182182

183183
# CHECK: {evex} shlx r11, r15, r9
184184
# CHECK: encoding: [0x62,0x52,0xb5,0x08,0xf7,0xdf]
185185
{evex} shlx r11, r15, r9
186186

187187
# CHECK: {evex} shlx r15, qword ptr [rax + 4*rbx + 123], r9
188-
# CHECK: encoding: [0x62,0x72,0xb5,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
188+
# CHECK: encoding: [0x62,0x72,0xb5,0x08,0xf7,0x7c,0x98,0x7b]
189189
{evex} shlx r15, qword ptr [rax + 4*rbx + 123], r9
190190

191191
# CHECK: shlx r26d, r22d, r18d
@@ -211,15 +211,15 @@
211211
{evex} shrx r10d, edx, ecx
212212

213213
# CHECK: {evex} shrx edx, dword ptr [rax + 4*rbx + 123], ecx
214-
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
214+
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf7,0x54,0x98,0x7b]
215215
{evex} shrx edx, dword ptr [rax + 4*rbx + 123], ecx
216216

217217
# CHECK: {evex} shrx r11, r15, r9
218218
# CHECK: encoding: [0x62,0x52,0xb7,0x08,0xf7,0xdf]
219219
{evex} shrx r11, r15, r9
220220

221221
# CHECK: {evex} shrx r15, qword ptr [rax + 4*rbx + 123], r9
222-
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
222+
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf7,0x7c,0x98,0x7b]
223223
{evex} shrx r15, qword ptr [rax + 4*rbx + 123], r9
224224

225225
# CHECK: shrx r26d, r22d, r18d

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