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LiqinWengLiqinWeng
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Rebase && fix the comments
1 parent 9499fed commit d50dd93

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4 files changed

+38
-42
lines changed

4 files changed

+38
-42
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 30 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1456,10 +1456,9 @@ InstructionCost VPWidenRecipe::computeCost(ElementCount VF,
14561456

14571457
void VPWidenEVLRecipe::execute(VPTransformState &State) {
14581458
unsigned Opcode = getOpcode();
1459-
// TODO: Support other opcodes
14601459
if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) {
1461-
Value *Op1 = State.get(getOperand(0), 0);
1462-
Value *Op2 = State.get(getOperand(1), 0);
1460+
Value *Op1 = State.get(getOperand(0));
1461+
Value *Op2 = State.get(getOperand(1));
14631462
auto &Ctx = State.Builder.getContext();
14641463
Value *Pred = MetadataAsValue::get(
14651464
Ctx, MDString::get(Ctx, CmpInst::getPredicateName(getPredicate())));
@@ -1472,46 +1471,45 @@ void VPWidenEVLRecipe::execute(VPTransformState &State) {
14721471
VectorType *RetType = VectorType::get(Type::getInt1Ty(Ctx), State.VF);
14731472
Value *VPInst = Builder.createVectorInstruction(Opcode, RetType,
14741473
{Op1, Op2, Pred}, "vp.op");
1475-
if (auto *VecOp = dyn_cast<CastInst>(VPInst))
1476-
VecOp->copyIRFlags(getUnderlyingInstr());
1474+
if (isa<FPMathOperator>(VPInst))
1475+
setFlags(cast<Instruction>(VPInst));
14771476

1478-
State.set(this, VPInst, 0);
1477+
State.set(this, VPInst);
14791478
State.addMetadata(VPInst,
14801479
dyn_cast_or_null<Instruction>(getUnderlyingValue()));
14811480
return;
14821481
}
14831482

1484-
if (!Instruction::isBinaryOp(Opcode) && !Instruction::isUnaryOp(Opcode))
1485-
llvm_unreachable("Unsupported opcode in VPWidenEVLRecipe::execute");
1483+
if (Instruction::isBinaryOp(Opcode) || Instruction::isUnaryOp(Opcode)) {
1484+
State.setDebugLocFrom(getDebugLoc());
14861485

1487-
State.setDebugLocFrom(getDebugLoc());
1488-
1489-
assert(State.get(getOperand(0))->getType()->isVectorTy() &&
1490-
"VPWidenEVLRecipe should not be used for scalars");
1486+
assert(State.get(getOperand(0))->getType()->isVectorTy() &&
1487+
"VPWidenEVLRecipe should not be used for scalars");
14911488

1492-
VPValue *EVL = getEVL();
1493-
Value *EVLArg = State.get(EVL, /*NeedsScalar=*/true);
1494-
IRBuilderBase &BuilderIR = State.Builder;
1495-
VectorBuilder Builder(BuilderIR);
1496-
Value *Mask = BuilderIR.CreateVectorSplat(State.VF, BuilderIR.getTrue());
1489+
VPValue *EVL = getEVL();
1490+
Value *EVLArg = State.get(EVL, /*NeedsScalar=*/true);
1491+
IRBuilderBase &BuilderIR = State.Builder;
1492+
VectorBuilder Builder(BuilderIR);
1493+
Value *Mask = BuilderIR.CreateVectorSplat(State.VF, BuilderIR.getTrue());
14971494

1498-
SmallVector<Value *, 4> Ops;
1499-
for (unsigned I = 0, E = getNumOperands() - 1; I < E; ++I) {
1500-
VPValue *VPOp = getOperand(I);
1501-
Ops.push_back(State.get(VPOp));
1502-
}
1495+
SmallVector<Value *, 4> Ops;
1496+
for (unsigned I = 0, E = getNumOperands() - 1; I < E; ++I) {
1497+
VPValue *VPOp = getOperand(I);
1498+
Ops.push_back(State.get(VPOp));
1499+
}
15031500

1504-
Builder.setMask(Mask).setEVL(EVLArg);
1505-
Value *VPInst =
1506-
Builder.createVectorInstruction(Opcode, Ops[0]->getType(), Ops, "vp.op");
1507-
// Currently vp-intrinsics only accept FMF flags.
1508-
// TODO: Enable other flags when support is added.
1509-
if (isa<FPMathOperator>(VPInst))
1510-
setFlags(cast<Instruction>(VPInst));
1501+
Builder.setMask(Mask).setEVL(EVLArg);
1502+
Value *VPInst = Builder.createVectorInstruction(Opcode, Ops[0]->getType(),
1503+
Ops, "vp.op");
1504+
// Currently vp-intrinsics only accept FMF flags.
1505+
// TODO: Enable other flags when support is added.
1506+
if (isa<FPMathOperator>(VPInst))
1507+
setFlags(cast<Instruction>(VPInst));
15111508

1512-
State.set(this, VPInst);
1513-
State.addMetadata(VPInst,
1514-
dyn_cast_or_null<Instruction>(getUnderlyingValue()));
1509+
State.set(this, VPInst);
1510+
State.addMetadata(VPInst,
1511+
dyn_cast_or_null<Instruction>(getUnderlyingValue()));
1512+
}
15151513
}
15161514

15171515
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1475,9 +1475,7 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) {
14751475
})
14761476
.Case<VPWidenRecipe>([&](VPWidenRecipe *W) -> VPRecipeBase * {
14771477
unsigned Opcode = W->getOpcode();
1478-
if (!Instruction::isBinaryOp(Opcode) &&
1479-
!Instruction::isUnaryOp(Opcode) &&
1480-
Opcode != Instruction::ICmp && Opcode != Instruction::FCmp)
1478+
if (Opcode == Instruction::Freeze)
14811479
return nullptr;
14821480
return new VPWidenEVLRecipe(*W, EVL);
14831481
})

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ define void @reverse_load_store_masked(i64 %startval, ptr noalias %ptr, ptr noal
143143
; IF-EVL-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[PTR:%.*]], i32 [[TMP7]]
144144
; IF-EVL-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP12]], i32 0
145145
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer), i32 [[TMP5]])
146-
; IF-EVL-NEXT: [[TMP14:%.*]] = icmp slt <vscale x 4 x i32> [[VP_OP_LOAD]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 100, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
146+
; IF-EVL-NEXT: [[TMP14:%.*]] = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i32(<vscale x 4 x i32> %vp.op.load, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 100, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer), metadata !"slt", <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer), i32 %5)
147147
; IF-EVL-NEXT: [[TMP15:%.*]] = select <vscale x 4 x i1> [[TMP10]], <vscale x 4 x i1> [[TMP14]], <vscale x 4 x i1> zeroinitializer
148148
; IF-EVL-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[PTR1:%.*]], i64 [[TMP11]]
149149
; IF-EVL-NEXT: [[TMP17:%.*]] = mul i64 0, [[TMP4]]

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cmp-intrinsics.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ define void @vp_icmp(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) {
1717
; IF-EVL: <x1> vector loop: {
1818
; IF-EVL-NEXT: vector.body:
1919
; IF-EVL-NEXT: EMIT vp<[[IV:%[0-9]+]]> = CANONICAL-INDUCTION
20-
; IF-EVL-NEXT: EXPLICIT-VECTOR-LENGTH-BASED-IV-PHI vp<[[EVL_PHI:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEX:%[0-9]+]]>
20+
; IF-EVL-NEXT: EXPLICIT-VECTOR-LENGTH-BASED-IV-PHI vp<[[EVL_PHI:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEXT:%.+]]>
2121
; IF-EVL-NEXT: EMIT vp<[[AVL:%.+]]> = sub ir<%N>, vp<[[EVL_PHI]]>
2222
; IF-EVL-NEXT: EMIT vp<[[EVL:%.+]]> = EXPLICIT-VECTOR-LENGTH vp<[[AVL]]>
2323
; IF-EVL-NEXT: vp<[[ST:%[0-9]+]]> = SCALAR-STEPS vp<[[EVL_PHI]]>, ir<1>
@@ -33,8 +33,8 @@ define void @vp_icmp(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) {
3333
; IF-EVL-NEXT: vp<[[PTR3:%[0-9]+]]> = vector-pointer ir<[[GEP3]]>
3434
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR3]]>, ir<[[ZEXT]]>, vp<[[EVL]]>
3535
; IF-EVL-NEXT: SCALAR-CAST vp<[[CAST:%[0-9]+]]> = zext vp<[[EVL]]> to i64
36-
; IF-EVL-NEXT: EMIT vp<[[IV_NEX]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
37-
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT:%[0-9]+]]> = add vp<[[IV]]>, vp<[[VFUF]]>
36+
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
37+
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT:%.+]]> = add vp<[[IV]]>, vp<[[VFUF]]>
3838
; IF-EVL-NEXT: EMIT branch-on-count vp<[[IV_NEXT_EXIT]]>, vp<[[VTC]]>
3939
; IF-EVL-NEXT: No successors
4040
; IF-EVL-NEXT: }
@@ -72,7 +72,7 @@ define void @vp_fcmp(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) {
7272
; IF-EVL: <x1> vector loop: {
7373
; IF-EVL-NEXT: vector.body:
7474
; IF-EVL-NEXT: EMIT vp<[[IV:%[0-9]+]]> = CANONICAL-INDUCTION
75-
; IF-EVL-NEXT: EXPLICIT-VECTOR-LENGTH-BASED-IV-PHI vp<[[EVL_PHI:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEX:%[0-9]+]]>
75+
; IF-EVL-NEXT: EXPLICIT-VECTOR-LENGTH-BASED-IV-PHI vp<[[EVL_PHI:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEXT:%.+]]>
7676
; IF-EVL-NEXT: EMIT vp<[[AVL:%.+]]> = sub ir<%N>, vp<[[EVL_PHI]]>
7777
; IF-EVL-NEXT: EMIT vp<[[EVL:%.+]]> = EXPLICIT-VECTOR-LENGTH vp<[[AVL]]>
7878
; IF-EVL-NEXT: vp<[[ST:%[0-9]+]]> = SCALAR-STEPS vp<[[EVL_PHI]]>, ir<1>
@@ -88,8 +88,8 @@ define void @vp_fcmp(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) {
8888
; IF-EVL-NEXT: vp<[[PTR3:%[0-9]+]]> = vector-pointer ir<[[GEP3]]>
8989
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR3]]>, ir<[[UITOFP]]>, vp<[[EVL]]>
9090
; IF-EVL-NEXT: SCALAR-CAST vp<[[CAST:%[0-9]+]]> = zext vp<[[EVL]]> to i64
91-
; IF-EVL-NEXT: EMIT vp<[[IV_NEX]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
92-
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT:%[0-9]+]]> = add vp<[[IV]]>, vp<[[VFUF]]>
91+
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
92+
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT:%.+]]> = add vp<[[IV]]>, vp<[[VFUF]]>
9393
; IF-EVL-NEXT: EMIT branch-on-count vp<[[IV_NEXT_EXIT]]>, vp<[[VTC]]>
9494
; IF-EVL-NEXT: No successors
9595
; IF-EVL-NEXT: }

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