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XinWang10XinWang10
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[X86] Support lowering for APX promoted BMI instructions.
1 parent e879002 commit d8d452a

12 files changed

+1222
-23
lines changed

‎llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Lines changed: 28 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -4087,14 +4087,17 @@ MachineSDNode *X86DAGToDAGISel::matchBEXTRFromAndImm(SDNode *Node) {
40874087
SDValue Control;
40884088
unsigned ROpc, MOpc;
40894089

4090+
#define GET_EGPR_IF_ENABLED(OPC) Subtarget->hasEGPR() ? OPC##_EVEX : OPC
40904091
if (!PreferBEXTR) {
40914092
assert(Subtarget->hasBMI2() && "We must have BMI2's BZHI then.");
40924093
// If we can't make use of BEXTR then we can't fuse shift+mask stages.
40934094
// Let's perform the mask first, and apply shift later. Note that we need to
40944095
// widen the mask to account for the fact that we'll apply shift afterwards!
40954096
Control = CurDAG->getTargetConstant(Shift + MaskSize, dl, NVT);
4096-
ROpc = NVT == MVT::i64 ? X86::BZHI64rr : X86::BZHI32rr;
4097-
MOpc = NVT == MVT::i64 ? X86::BZHI64rm : X86::BZHI32rm;
4097+
ROpc = NVT == MVT::i64 ? GET_EGPR_IF_ENABLED(X86::BZHI64rr)
4098+
: GET_EGPR_IF_ENABLED(X86::BZHI32rr);
4099+
MOpc = NVT == MVT::i64 ? GET_EGPR_IF_ENABLED(X86::BZHI64rm)
4100+
: GET_EGPR_IF_ENABLED(X86::BZHI32rm);
40984101
unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri;
40994102
Control = SDValue(CurDAG->getMachineNode(NewOpc, dl, NVT, Control), 0);
41004103
} else {
@@ -4109,12 +4112,15 @@ MachineSDNode *X86DAGToDAGISel::matchBEXTRFromAndImm(SDNode *Node) {
41094112
} else {
41104113
assert(Subtarget->hasBMI() && "We must have BMI1's BEXTR then.");
41114114
// BMI requires the immediate to placed in a register.
4112-
ROpc = NVT == MVT::i64 ? X86::BEXTR64rr : X86::BEXTR32rr;
4113-
MOpc = NVT == MVT::i64 ? X86::BEXTR64rm : X86::BEXTR32rm;
4115+
ROpc = NVT == MVT::i64 ? GET_EGPR_IF_ENABLED(X86::BEXTR64rr)
4116+
: GET_EGPR_IF_ENABLED(X86::BEXTR32rr);
4117+
MOpc = NVT == MVT::i64 ? GET_EGPR_IF_ENABLED(X86::BEXTR64rm)
4118+
: GET_EGPR_IF_ENABLED(X86::BEXTR32rm);
41144119
unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri;
41154120
Control = SDValue(CurDAG->getMachineNode(NewOpc, dl, NVT, Control), 0);
41164121
}
41174122
}
4123+
#undef GET_EGPR_IF_ENABLED
41184124

41194125
MachineSDNode *NewNode;
41204126
SDValue Input = N0->getOperand(0);
@@ -5482,26 +5488,32 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
54825488
bool UseMULXHi = UseMULX && SDValue(Node, 0).use_empty();
54835489
switch (NVT.SimpleTy) {
54845490
default: llvm_unreachable("Unsupported VT!");
5491+
#define GET_EGPR_IF_ENABLED(OPC) Subtarget->hasEGPR() ? OPC##_EVEX : OPC
54855492
case MVT::i32:
5486-
Opc = UseMULXHi ? X86::MULX32Hrr :
5487-
UseMULX ? X86::MULX32rr :
5488-
IsSigned ? X86::IMUL32r : X86::MUL32r;
5489-
MOpc = UseMULXHi ? X86::MULX32Hrm :
5490-
UseMULX ? X86::MULX32rm :
5491-
IsSigned ? X86::IMUL32m : X86::MUL32m;
5493+
Opc = UseMULXHi ? X86::MULX32Hrr
5494+
: UseMULX ? GET_EGPR_IF_ENABLED(X86::MULX32rr)
5495+
: IsSigned ? X86::IMUL32r
5496+
: X86::MUL32r;
5497+
MOpc = UseMULXHi ? X86::MULX32Hrm
5498+
: UseMULX ? GET_EGPR_IF_ENABLED(X86::MULX32rm)
5499+
: IsSigned ? X86::IMUL32m
5500+
: X86::MUL32m;
54925501
LoReg = UseMULX ? X86::EDX : X86::EAX;
54935502
HiReg = X86::EDX;
54945503
break;
54955504
case MVT::i64:
5496-
Opc = UseMULXHi ? X86::MULX64Hrr :
5497-
UseMULX ? X86::MULX64rr :
5498-
IsSigned ? X86::IMUL64r : X86::MUL64r;
5499-
MOpc = UseMULXHi ? X86::MULX64Hrm :
5500-
UseMULX ? X86::MULX64rm :
5501-
IsSigned ? X86::IMUL64m : X86::MUL64m;
5505+
Opc = UseMULXHi ? X86::MULX64Hrr
5506+
: UseMULX ? GET_EGPR_IF_ENABLED(X86::MULX64rr)
5507+
: IsSigned ? X86::IMUL64r
5508+
: X86::MUL64r;
5509+
MOpc = UseMULXHi ? X86::MULX64Hrm
5510+
: UseMULX ? GET_EGPR_IF_ENABLED(X86::MULX64rm)
5511+
: IsSigned ? X86::IMUL64m
5512+
: X86::MUL64m;
55025513
LoReg = UseMULX ? X86::RDX : X86::RAX;
55035514
HiReg = X86::RDX;
55045515
break;
5516+
#undef GET_EGPR_IF_ENABLED
55055517
}
55065518

55075519
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;

‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1338,7 +1338,7 @@ defm ANDN32 : AndN<Xi32, "_EVEX">, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]
13381338
defm ANDN64 : AndN<Xi64, "_EVEX">, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>;
13391339
}
13401340

1341-
let Predicates = [HasBMI], AddedComplexity = -6 in {
1341+
let Predicates = [HasBMI, NoEGPR], AddedComplexity = -6 in {
13421342
def : Pat<(and (not GR32:$src1), GR32:$src2),
13431343
(ANDN32rr GR32:$src1, GR32:$src2)>;
13441344
def : Pat<(and (not GR64:$src1), GR64:$src2),
@@ -1349,6 +1349,17 @@ let Predicates = [HasBMI], AddedComplexity = -6 in {
13491349
(ANDN64rm GR64:$src1, addr:$src2)>;
13501350
}
13511351

1352+
let Predicates = [HasBMI, HasEGPR], AddedComplexity = -6 in {
1353+
def : Pat<(and (not GR32:$src1), GR32:$src2),
1354+
(ANDN32rr_EVEX GR32:$src1, GR32:$src2)>;
1355+
def : Pat<(and (not GR64:$src1), GR64:$src2),
1356+
(ANDN64rr_EVEX GR64:$src1, GR64:$src2)>;
1357+
def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)),
1358+
(ANDN32rm_EVEX GR32:$src1, addr:$src2)>;
1359+
def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)),
1360+
(ANDN64rm_EVEX GR64:$src1, addr:$src2)>;
1361+
}
1362+
13521363
//===----------------------------------------------------------------------===//
13531364
// MULX Instruction
13541365
//

‎llvm/lib/Target/X86/X86InstrCompiler.td

Lines changed: 59 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1864,7 +1864,7 @@ def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)),
18641864
def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)),
18651865
(SHRD64rrCL GR64:$src1, GR64:$src2)>;
18661866

1867-
let Predicates = [HasBMI2] in {
1867+
let Predicates = [HasBMI2, NoEGPR] in {
18681868
let AddedComplexity = 1 in {
18691869
def : Pat<(sra GR32:$src1, (shiftMask32 GR8:$src2)),
18701870
(SARX32rr GR32:$src1,
@@ -1922,6 +1922,64 @@ let Predicates = [HasBMI2] in {
19221922
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
19231923
}
19241924

1925+
let Predicates = [HasBMI2, HasEGPR] in {
1926+
let AddedComplexity = 1 in {
1927+
def : Pat<(sra GR32:$src1, (shiftMask32 GR8:$src2)),
1928+
(SARX32rr_EVEX GR32:$src1,
1929+
(INSERT_SUBREG
1930+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1931+
def : Pat<(sra GR64:$src1, (shiftMask64 GR8:$src2)),
1932+
(SARX64rr_EVEX GR64:$src1,
1933+
(INSERT_SUBREG
1934+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1935+
1936+
def : Pat<(srl GR32:$src1, (shiftMask32 GR8:$src2)),
1937+
(SHRX32rr_EVEX GR32:$src1,
1938+
(INSERT_SUBREG
1939+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1940+
def : Pat<(srl GR64:$src1, (shiftMask64 GR8:$src2)),
1941+
(SHRX64rr_EVEX GR64:$src1,
1942+
(INSERT_SUBREG
1943+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1944+
1945+
def : Pat<(shl GR32:$src1, (shiftMask32 GR8:$src2)),
1946+
(SHLX32rr_EVEX GR32:$src1,
1947+
(INSERT_SUBREG
1948+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1949+
def : Pat<(shl GR64:$src1, (shiftMask64 GR8:$src2)),
1950+
(SHLX64rr_EVEX GR64:$src1,
1951+
(INSERT_SUBREG
1952+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1953+
}
1954+
1955+
def : Pat<(sra (loadi32 addr:$src1), (shiftMask32 GR8:$src2)),
1956+
(SARX32rm_EVEX addr:$src1,
1957+
(INSERT_SUBREG
1958+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1959+
def : Pat<(sra (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
1960+
(SARX64rm_EVEX addr:$src1,
1961+
(INSERT_SUBREG
1962+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1963+
1964+
def : Pat<(srl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)),
1965+
(SHRX32rm_EVEX addr:$src1,
1966+
(INSERT_SUBREG
1967+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1968+
def : Pat<(srl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
1969+
(SHRX64rm_EVEX addr:$src1,
1970+
(INSERT_SUBREG
1971+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1972+
1973+
def : Pat<(shl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)),
1974+
(SHLX32rm_EVEX addr:$src1,
1975+
(INSERT_SUBREG
1976+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1977+
def : Pat<(shl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
1978+
(SHLX64rm_EVEX addr:$src1,
1979+
(INSERT_SUBREG
1980+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1981+
}
1982+
19251983
// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location.
19261984
multiclass one_bit_patterns<RegisterClass RC, ValueType VT, Instruction BTR,
19271985
Instruction BTS, Instruction BTC,

‎llvm/lib/Target/X86/X86InstrMisc.td

Lines changed: 58 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1241,7 +1241,7 @@ let Predicates = [HasBMI, In64BitMode], Defs = [EFLAGS] in {
12411241
defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64, "_EVEX">, EVEX;
12421242
}
12431243

1244-
let Predicates = [HasBMI] in {
1244+
let Predicates = [HasBMI, NoEGPR] in {
12451245
// FIXME(1): patterns for the load versions are not implemented
12461246
// FIXME(2): By only matching `add_su` and `ineg_su` we may emit
12471247
// extra `mov` instructions if `src` has future uses. It may be better
@@ -1278,6 +1278,39 @@ let Predicates = [HasBMI] in {
12781278
(BLSI64rr GR64:$src)>;
12791279
}
12801280

1281+
let Predicates = [HasBMI, HasEGPR] in {
1282+
def : Pat<(and GR32:$src, (add_su GR32:$src, -1)),
1283+
(BLSR32rr_EVEX GR32:$src)>;
1284+
def : Pat<(and GR64:$src, (add_su GR64:$src, -1)),
1285+
(BLSR64rr_EVEX GR64:$src)>;
1286+
1287+
def : Pat<(xor GR32:$src, (add_su GR32:$src, -1)),
1288+
(BLSMSK32rr_EVEX GR32:$src)>;
1289+
def : Pat<(xor GR64:$src, (add_su GR64:$src, -1)),
1290+
(BLSMSK64rr_EVEX GR64:$src)>;
1291+
1292+
def : Pat<(and GR32:$src, (ineg_su GR32:$src)),
1293+
(BLSI32rr_EVEX GR32:$src)>;
1294+
def : Pat<(and GR64:$src, (ineg_su GR64:$src)),
1295+
(BLSI64rr_EVEX GR64:$src)>;
1296+
1297+
// Versions to match flag producing ops.
1298+
def : Pat<(and_flag_nocf GR32:$src, (add_su GR32:$src, -1)),
1299+
(BLSR32rr_EVEX GR32:$src)>;
1300+
def : Pat<(and_flag_nocf GR64:$src, (add_su GR64:$src, -1)),
1301+
(BLSR64rr_EVEX GR64:$src)>;
1302+
1303+
def : Pat<(xor_flag_nocf GR32:$src, (add_su GR32:$src, -1)),
1304+
(BLSMSK32rr_EVEX GR32:$src)>;
1305+
def : Pat<(xor_flag_nocf GR64:$src, (add_su GR64:$src, -1)),
1306+
(BLSMSK64rr_EVEX GR64:$src)>;
1307+
1308+
def : Pat<(and_flag_nocf GR32:$src, (ineg_su GR32:$src)),
1309+
(BLSI32rr_EVEX GR32:$src)>;
1310+
def : Pat<(and_flag_nocf GR64:$src, (ineg_su GR64:$src)),
1311+
(BLSI64rr_EVEX GR64:$src)>;
1312+
}
1313+
12811314
multiclass Bmi4VOp3<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node,
12821315
X86FoldableSchedWrite sched, string Suffix = ""> {
12831316
let SchedRW = [sched], Form = MRMSrcReg4VOp3 in
@@ -1324,7 +1357,7 @@ def AndMask64 : ImmLeaf<i64, [{
13241357
}]>;
13251358

13261359
// Use BEXTR for 64-bit 'and' with large immediate 'mask'.
1327-
let Predicates = [HasBMI, NoBMI2, NoTBM] in {
1360+
let Predicates = [HasBMI, NoBMI2, NoTBM, NoEGPR] in {
13281361
def : Pat<(and GR64:$src, AndMask64:$mask),
13291362
(BEXTR64rr GR64:$src,
13301363
(SUBREG_TO_REG (i64 0),
@@ -1335,8 +1368,19 @@ let Predicates = [HasBMI, NoBMI2, NoTBM] in {
13351368
(MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>;
13361369
}
13371370

1371+
let Predicates = [HasBMI, NoBMI2, NoTBM, HasEGPR] in {
1372+
def : Pat<(and GR64:$src, AndMask64:$mask),
1373+
(BEXTR64rr_EVEX GR64:$src,
1374+
(SUBREG_TO_REG (i64 0),
1375+
(MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>;
1376+
def : Pat<(and (loadi64 addr:$src), AndMask64:$mask),
1377+
(BEXTR64rm_EVEX addr:$src,
1378+
(SUBREG_TO_REG (i64 0),
1379+
(MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>;
1380+
}
1381+
13381382
// Use BZHI for 64-bit 'and' with large immediate 'mask'.
1339-
let Predicates = [HasBMI2, NoTBM] in {
1383+
let Predicates = [HasBMI2, NoTBM, NoEGPR] in {
13401384
def : Pat<(and GR64:$src, AndMask64:$mask),
13411385
(BZHI64rr GR64:$src,
13421386
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
@@ -1347,6 +1391,17 @@ let Predicates = [HasBMI2, NoTBM] in {
13471391
(MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
13481392
}
13491393

1394+
let Predicates = [HasBMI2, NoTBM, HasEGPR] in {
1395+
def : Pat<(and GR64:$src, AndMask64:$mask),
1396+
(BZHI64rr_EVEX GR64:$src,
1397+
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1398+
(MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
1399+
def : Pat<(and (loadi64 addr:$src), AndMask64:$mask),
1400+
(BZHI64rm_EVEX addr:$src,
1401+
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1402+
(MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
1403+
}
1404+
13501405
multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
13511406
X86MemOperand x86memop, SDPatternOperator OpNode,
13521407
PatFrag ld_frag, string Suffix = ""> {

‎llvm/lib/Target/X86/X86InstrShiftRotate.td

Lines changed: 81 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -879,7 +879,7 @@ let Predicates = [HasBMI2, HasEGPR, In64BitMode] in {
879879
defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem, "_EVEX">, T8, PD, REX_W, EVEX;
880880
}
881881

882-
let Predicates = [HasBMI2] in {
882+
let Predicates = [HasBMI2, NoEGPR] in {
883883
// Prefer RORX which is non-destructive and doesn't update EFLAGS.
884884
let AddedComplexity = 10 in {
885885
def : Pat<(rotr GR32:$src, (i8 imm:$shamt)),
@@ -983,6 +983,86 @@ let Predicates = [HasBMI2] in {
983983
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
984984
}
985985

986+
let Predicates = [HasBMI2, HasEGPR] in {
987+
let AddedComplexity = 10 in {
988+
def : Pat<(rotr GR32:$src, (i8 imm:$shamt)),
989+
(RORX32ri_EVEX GR32:$src, imm:$shamt)>;
990+
def : Pat<(rotr GR64:$src, (i8 imm:$shamt)),
991+
(RORX64ri_EVEX GR64:$src, imm:$shamt)>;
992+
993+
def : Pat<(rotl GR32:$src, (i8 imm:$shamt)),
994+
(RORX32ri_EVEX GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
995+
def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
996+
(RORX64ri_EVEX GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
997+
}
998+
999+
def : Pat<(rotr (loadi32 addr:$src), (i8 imm:$shamt)),
1000+
(RORX32mi_EVEX addr:$src, imm:$shamt)>;
1001+
def : Pat<(rotr (loadi64 addr:$src), (i8 imm:$shamt)),
1002+
(RORX64mi_EVEX addr:$src, imm:$shamt)>;
1003+
1004+
def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)),
1005+
(RORX32mi_EVEX addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
1006+
def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
1007+
(RORX64mi_EVEX addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
1008+
1009+
let AddedComplexity = 1 in {
1010+
def : Pat<(sra GR32:$src1, GR8:$src2),
1011+
(SARX32rr_EVEX GR32:$src1,
1012+
(INSERT_SUBREG
1013+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1014+
def : Pat<(sra GR64:$src1, GR8:$src2),
1015+
(SARX64rr_EVEX GR64:$src1,
1016+
(INSERT_SUBREG
1017+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1018+
1019+
def : Pat<(srl GR32:$src1, GR8:$src2),
1020+
(SHRX32rr_EVEX GR32:$src1,
1021+
(INSERT_SUBREG
1022+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1023+
def : Pat<(srl GR64:$src1, GR8:$src2),
1024+
(SHRX64rr_EVEX GR64:$src1,
1025+
(INSERT_SUBREG
1026+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1027+
1028+
def : Pat<(shl GR32:$src1, GR8:$src2),
1029+
(SHLX32rr_EVEX GR32:$src1,
1030+
(INSERT_SUBREG
1031+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1032+
def : Pat<(shl GR64:$src1, GR8:$src2),
1033+
(SHLX64rr_EVEX GR64:$src1,
1034+
(INSERT_SUBREG
1035+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1036+
}
1037+
1038+
def : Pat<(sra (loadi32 addr:$src1), GR8:$src2),
1039+
(SARX32rm_EVEX addr:$src1,
1040+
(INSERT_SUBREG
1041+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1042+
def : Pat<(sra (loadi64 addr:$src1), GR8:$src2),
1043+
(SARX64rm_EVEX addr:$src1,
1044+
(INSERT_SUBREG
1045+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1046+
1047+
def : Pat<(srl (loadi32 addr:$src1), GR8:$src2),
1048+
(SHRX32rm_EVEX addr:$src1,
1049+
(INSERT_SUBREG
1050+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1051+
def : Pat<(srl (loadi64 addr:$src1), GR8:$src2),
1052+
(SHRX64rm_EVEX addr:$src1,
1053+
(INSERT_SUBREG
1054+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1055+
1056+
def : Pat<(shl (loadi32 addr:$src1), GR8:$src2),
1057+
(SHLX32rm_EVEX addr:$src1,
1058+
(INSERT_SUBREG
1059+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1060+
def : Pat<(shl (loadi64 addr:$src1), GR8:$src2),
1061+
(SHLX64rm_EVEX addr:$src1,
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(INSERT_SUBREG
1063+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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}
1065+
9861066
def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)),
9871067
(ROL8ri GR8:$src1, relocImm:$src2)>;
9881068
def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)),

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