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4 files changed

+36
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‎llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4119,7 +4119,6 @@ MachineSDNode *X86DAGToDAGISel::matchBEXTRFromAndImm(SDNode *Node) {
41194119
Control = SDValue(CurDAG->getMachineNode(NewOpc, dl, NVT, Control), 0);
41204120
}
41214121
}
4122-
#undef GET_EGPR_IF_ENABLED
41234122

41244123
MachineSDNode *NewNode;
41254124
SDValue Input = N0->getOperand(0);
@@ -5487,7 +5486,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
54875486
bool UseMULXHi = UseMULX && SDValue(Node, 0).use_empty();
54885487
switch (NVT.SimpleTy) {
54895488
default: llvm_unreachable("Unsupported VT!");
5490-
#define GET_EGPR_IF_ENABLED(OPC) (Subtarget->hasEGPR() ? OPC##_EVEX : OPC)
54915489
case MVT::i32:
54925490
Opc = UseMULXHi ? X86::MULX32Hrr
54935491
: UseMULX ? GET_EGPR_IF_ENABLED(X86::MULX32rr)

‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1338,24 +1338,22 @@ defm ANDN32 : AndN<Xi32, "_EVEX">, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]
13381338
defm ANDN64 : AndN<Xi64, "_EVEX">, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>;
13391339
}
13401340

1341-
multiclass Andn_patterns<string Suffix = ""> {
1341+
multiclass Andn_Pats<string suffix> {
13421342
def : Pat<(and (not GR32:$src1), GR32:$src2),
1343-
(!cast<Instruction>(ANDN32rr#Suffix) GR32:$src1, GR32:$src2)>;
1343+
(!cast<Instruction>(ANDN32rr#suffix) GR32:$src1, GR32:$src2)>;
13441344
def : Pat<(and (not GR64:$src1), GR64:$src2),
1345-
(!cast<Instruction>(ANDN64rr#Suffix) GR64:$src1, GR64:$src2)>;
1345+
(!cast<Instruction>(ANDN64rr#suffix) GR64:$src1, GR64:$src2)>;
13461346
def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)),
1347-
(!cast<Instruction>(ANDN32rm#Suffix) GR32:$src1, addr:$src2)>;
1347+
(!cast<Instruction>(ANDN32rm#suffix) GR32:$src1, addr:$src2)>;
13481348
def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)),
1349-
(!cast<Instruction>(ANDN64rm#Suffix) GR64:$src1, addr:$src2)>;
1349+
(!cast<Instruction>(ANDN64rm#suffix) GR64:$src1, addr:$src2)>;
13501350
}
13511351

1352-
let Predicates = [HasBMI, NoEGPR], AddedComplexity = -6 in {
1353-
defm : Andn_patterns<>;
1354-
}
1352+
let Predicates = [HasBMI, NoEGPR], AddedComplexity = -6 in
1353+
defm : Andn_Pats<"">;
13551354

1356-
let Predicates = [HasBMI, HasEGPR], AddedComplexity = -6 in {
1357-
defm : Andn_patterns<"_EVEX">;
1358-
}
1355+
let Predicates = [HasBMI, HasEGPR], AddedComplexity = -6 in
1356+
defm : Andn_Pats<"_EVEX">;
13591357

13601358
//===----------------------------------------------------------------------===//
13611359
// MULX Instruction

‎llvm/lib/Target/X86/X86InstrMisc.td

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1241,48 +1241,48 @@ let Predicates = [HasBMI, In64BitMode], Defs = [EFLAGS] in {
12411241
defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64, "_EVEX">, EVEX;
12421242
}
12431243

1244-
multiclass Bls_patterns<string Suffix = ""> {
1244+
multiclass Bls_Pats<string suffix> {
12451245
// FIXME(1): patterns for the load versions are not implemented
12461246
// FIXME(2): By only matching `add_su` and `ineg_su` we may emit
12471247
// extra `mov` instructions if `src` has future uses. It may be better
12481248
// to always match if `src` has more users.
12491249
def : Pat<(and GR32:$src, (add_su GR32:$src, -1)),
1250-
(!cast<Instruction>(BLSR32rr#Suffix) GR32:$src)>;
1250+
(!cast<Instruction>(BLSR32rr#suffix) GR32:$src)>;
12511251
def : Pat<(and GR64:$src, (add_su GR64:$src, -1)),
1252-
(!cast<Instruction>(BLSR64rr#Suffix) GR64:$src)>;
1252+
(!cast<Instruction>(BLSR64rr#suffix) GR64:$src)>;
12531253

12541254
def : Pat<(xor GR32:$src, (add_su GR32:$src, -1)),
1255-
(!cast<Instruction>(BLSMSK32rr#Suffix) GR32:$src)>;
1255+
(!cast<Instruction>(BLSMSK32rr#suffix) GR32:$src)>;
12561256
def : Pat<(xor GR64:$src, (add_su GR64:$src, -1)),
1257-
(!cast<Instruction>(BLSMSK64rr#Suffix) GR64:$src)>;
1257+
(!cast<Instruction>(BLSMSK64rr#suffix) GR64:$src)>;
12581258

12591259
def : Pat<(and GR32:$src, (ineg_su GR32:$src)),
1260-
(!cast<Instruction>(BLSI32rr#Suffix) GR32:$src)>;
1260+
(!cast<Instruction>(BLSI32rr#suffix) GR32:$src)>;
12611261
def : Pat<(and GR64:$src, (ineg_su GR64:$src)),
1262-
(!cast<Instruction>(BLSI64rr#Suffix) GR64:$src)>;
1262+
(!cast<Instruction>(BLSI64rr#suffix) GR64:$src)>;
12631263

12641264
// Versions to match flag producing ops.
12651265
def : Pat<(and_flag_nocf GR32:$src, (add_su GR32:$src, -1)),
1266-
(!cast<Instruction>(BLSR32rr#Suffix) GR32:$src)>;
1266+
(!cast<Instruction>(BLSR32rr#suffix) GR32:$src)>;
12671267
def : Pat<(and_flag_nocf GR64:$src, (add_su GR64:$src, -1)),
1268-
(!cast<Instruction>(BLSR64rr#Suffix) GR64:$src)>;
1268+
(!cast<Instruction>(BLSR64rr#suffix) GR64:$src)>;
12691269

12701270
def : Pat<(xor_flag_nocf GR32:$src, (add_su GR32:$src, -1)),
1271-
(!cast<Instruction>(BLSMSK32rr#Suffix) GR32:$src)>;
1271+
(!cast<Instruction>(BLSMSK32rr#suffix) GR32:$src)>;
12721272
def : Pat<(xor_flag_nocf GR64:$src, (add_su GR64:$src, -1)),
1273-
(!cast<Instruction>(BLSMSK64rr#Suffix) GR64:$src)>;
1273+
(!cast<Instruction>(BLSMSK64rr#suffix) GR64:$src)>;
12741274

12751275
def : Pat<(and_flag_nocf GR32:$src, (ineg_su GR32:$src)),
1276-
(!cast<Instruction>(BLSI32rr#Suffix) GR32:$src)>;
1276+
(!cast<Instruction>(BLSI32rr#suffix) GR32:$src)>;
12771277
def : Pat<(and_flag_nocf GR64:$src, (ineg_su GR64:$src)),
1278-
(!cast<Instruction>(BLSI64rr#Suffix) GR64:$src)>;
1278+
(!cast<Instruction>(BLSI64rr#suffix) GR64:$src)>;
12791279
}
12801280

12811281
let Predicates = [HasBMI, NoEGPR] in
1282-
defm : Bls_patterns<>;
1282+
defm : Bls_Pats<"">;
12831283

12841284
let Predicates = [HasBMI, HasEGPR] in
1285-
defm : Bls_patterns<"_EVEX">;
1285+
defm : Bls_Pats<"_EVEX">;
12861286

12871287
multiclass Bmi4VOp3<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node,
12881288
X86FoldableSchedWrite sched, string Suffix = ""> {

‎llvm/lib/Target/X86/X86InstrShiftRotate.td

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,7 @@ multiclass ShiftX_Pats<SDNode op> {
348348
//
349349
// This priority is enforced by IsProfitableToFoldLoad.
350350
def : Pat<(op (loadi32 addr:$src1), GR8:$src2),
351+
<<<<<<< HEAD
351352
(!cast<Instruction>(NAME#"32rm") addr:$src1,
352353
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
353354
def : Pat<(op (loadi64 addr:$src1), GR8:$src2),
@@ -358,7 +359,6 @@ multiclass ShiftX_Pats<SDNode op> {
358359
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
359360
def : Pat<(op (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
360361
(!cast<Instruction>(NAME#"64rm") addr:$src1,
361-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
362362
}
363363

364364
let Predicates = [HasBMI2] in {
@@ -367,3 +367,14 @@ let Predicates = [HasBMI2] in {
367367
defm SHRX : ShiftX_Pats<srl>;
368368
defm SHLX : ShiftX_Pats<shl>;
369369
}
370+
=======
371+
(!cast<Instruction>(NAME#"32rm"#suffix) addr:$src1,
372+
(INSERT_SUBREG
373+
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
374+
def : Pat<(op (loadi64 addr:$src1), GR8:$src2),
375+
(!cast<Instruction>(NAME#"64rm"#suffix) addr:$src1,
376+
(INSERT_SUBREG
377+
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
378+
}
379+
380+
multiclass RORX_Pats<string suffix> {

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