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[Sparc] Remove LEA instructions (NFCI) (#65850)
LEA_ADDri and LEAX_ADDri are printed / encoded the same way as ADDri. I had to change the type of simm13Op so that it can be used in both 32- and 64-bit modes. This required the changes in operands of some InstAliases.
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+35
-50
lines changed

7 files changed

+35
-50
lines changed

‎llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -342,7 +342,7 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address,
342342

343343
static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
344344
const MCDisassembler *Decoder) {
345-
unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
346-
MI.addOperand(MCOperand::createImm(tgt));
345+
assert(isUInt<13>(insn));
346+
MI.addOperand(MCOperand::createImm(SignExtend64<13>(insn)));
347347
return MCDisassembler::Success;
348348
}

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp

+1-9
Original file line numberDiff line numberDiff line change
@@ -148,15 +148,7 @@ void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
148148

149149
void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
150150
const MCSubtargetInfo &STI,
151-
raw_ostream &O, const char *Modifier) {
152-
// If this is an ADD operand, emit it like normal operands.
153-
if (Modifier && !strcmp(Modifier, "arith")) {
154-
printOperand(MI, opNum, STI, O);
155-
O << ", ";
156-
printOperand(MI, opNum + 1, STI, O);
157-
return;
158-
}
159-
151+
raw_ostream &O) {
160152
const MCOperand &Op1 = MI->getOperand(opNum);
161153
const MCOperand &Op2 = MI->getOperand(opNum + 1);
162154

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ class SparcInstPrinter : public MCInstPrinter {
4747
void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
4848
raw_ostream &OS);
4949
void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
50-
raw_ostream &OS, const char *Modifier = nullptr);
50+
raw_ostream &OS);
5151
void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
5252
raw_ostream &OS);
5353
bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,

‎llvm/lib/Target/Sparc/SparcInstr64Bit.td

-6
Original file line numberDiff line numberDiff line change
@@ -171,12 +171,6 @@ def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
171171
"add $rs1, $rs2, $rd, $sym",
172172
[(set i64:$rd,
173173
(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
174-
175-
// "LEA" form of add
176-
def LEAX_ADDri : F3_2<2, 0b000000,
177-
(outs I64Regs:$rd), (ins (MEMri $rs1, $simm13):$addr),
178-
"add ${addr:arith}, $rd",
179-
[(set iPTR:$rd, ADDRri:$addr)]>;
180174
}
181175

182176
def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;

‎llvm/lib/Target/Sparc/SparcInstrAliases.td

+19-19
Original file line numberDiff line numberDiff line change
@@ -486,41 +486,41 @@ let Predicates = [HasV9] in {
486486
def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
487487

488488
// inc simm13, rd -> add rd, simm13, rd
489-
def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
489+
def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
490490

491491
// inccc rd -> addcc rd, 1, rd
492492
def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
493493

494494
// inccc simm13, rd -> addcc rd, simm13, rd
495-
def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
495+
def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
496496

497497
// dec rd -> sub rd, 1, rd
498498
def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
499499

500500
// dec simm13, rd -> sub rd, simm13, rd
501-
def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
501+
def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
502502

503503
// deccc rd -> subcc rd, 1, rd
504504
def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
505505

506506
// deccc simm13, rd -> subcc rd, simm13, rd
507-
def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
507+
def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
508508

509509
// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0
510510
def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
511-
def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
511+
def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, simm13Op:$simm13), 0>;
512512

513513
// bset reg_or_imm, rd -> or rd,reg_or_imm,rd
514514
def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
515-
def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
515+
def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
516516

517517
// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
518518
def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
519-
def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
519+
def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
520520

521521
// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
522522
def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
523-
def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
523+
def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
524524

525525

526526
// clr rd -> or %g0, %g0, rd
@@ -537,7 +537,7 @@ def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;
537537

538538
// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
539539
def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
540-
def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
540+
def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, simm13Op:$simm13)>;
541541

542542
// mov specialreg, rd -> rd specialreg, rd
543543
def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
@@ -547,13 +547,13 @@ def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
547547

548548
// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
549549
def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
550-
def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
550+
def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
551551
def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
552-
def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
552+
def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, simm13Op:$simm13), 0>;
553553
def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
554-
def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
554+
def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, simm13Op:$simm13), 0>;
555555
def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
556-
def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
556+
def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;
557557

558558
// End of Section A.3
559559

@@ -566,23 +566,23 @@ let EmitPriority = 0 in
566566
// (aka: omit the first arg when it's g0. This is not in the manual, but is
567567
// supported by gnu and solaris as)
568568
def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
569-
def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
569+
def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
570570
def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
571-
def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
571+
def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, simm13Op:$simm13), 0>;
572572
def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
573-
def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
573+
def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, simm13Op:$simm13), 0>;
574574
def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
575-
def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
575+
def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;
576576

577577
def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>;
578-
def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, i32imm:$simm13), 0>;
578+
def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, simm13Op:$simm13), 0>;
579579

580580
// wrpr %reg, %rd -> wrpr %reg, %g0, %rd
581581
// wrpr imm, %rd -> wrpr %g0, imm, %rd
582582
// Nonstandard GNU extensions.
583583
let Predicates = [HasV9] in {
584584
def : InstAlias<"wrpr $rs1, $rd", (WRPRrr PRRegs:$rd, IntRegs:$rs1, G0), 0>;
585-
def : InstAlias<"wrpr $simm13, $rd", (WRPRri PRRegs:$rd, G0, i32imm:$simm13), 0>;
585+
def : InstAlias<"wrpr $simm13, $rd", (WRPRri PRRegs:$rd, G0, simm13Op:$simm13), 0>;
586586
}
587587

588588
// flush -> flush %g0

‎llvm/lib/Target/Sparc/SparcInstrInfo.td

+8-9
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ def SETHIimm_not : PatLeaf<(i32 imm), [{
117117

118118
// Addressing modes.
119119
def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
120-
def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
120+
def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [], []>;
121121

122122
// Constrained operands for the shift operations.
123123
class ShiftAmtImmAsmOperand<int Bits> : AsmOperandClass {
@@ -221,7 +221,7 @@ def calltarget : Operand<i32> {
221221
let ParserMatchClass = SparcCallTargetAsmOperand;
222222
}
223223

224-
def simm13Op : Operand<i32> {
224+
def simm13Op : Operand<iPTR> {
225225
let DecoderMethod = "DecodeSIMM13";
226226
let EncoderMethod = "getSImm13OpValue";
227227
}
@@ -815,13 +815,6 @@ defm SRA : F3_S<"sra", 0b100111, 0, sra, i32, shift_imm5, IntRegs>;
815815
// Section B.13 - Add Instructions, p. 108
816816
defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
817817

818-
// "LEA" forms of add (patterns to make tblgen happy)
819-
let Predicates = [Is32Bit], isCodeGenOnly = 1 in
820-
def LEA_ADDri : F3_2<2, 0b000000,
821-
(outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
822-
"add ${addr:arith}, $rd",
823-
[(set iPTR:$rd, ADDRri:$addr)]>;
824-
825818
let Defs = [ICC] in
826819
defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
827820

@@ -1831,6 +1824,12 @@ def : Pat<(i32 simm13:$val),
18311824
def : Pat<(i32 imm:$val),
18321825
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
18331826

1827+
// Frame index.
1828+
def to_tframeindex : SDNodeXForm<frameindex, [{
1829+
return CurDAG->getTargetFrameIndex(N->getIndex(), N->getValueType(0));
1830+
}]>;
1831+
def : Pat<(i32 (frameindex:$ptr)), (ADDri (i32 (to_tframeindex $ptr)), (i32 0))>;
1832+
def : Pat<(i64 (frameindex:$ptr)), (ADDri (i64 (to_tframeindex $ptr)), (i64 0))>;
18341833

18351834
// Global addresses, constant pool entries
18361835
let Predicates = [Is32Bit] in {

‎llvm/test/CodeGen/SPARC/fp128-split.ll

+4-4
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ define fp128 @testcase(fp128 %0) {
1111
; CHECK: liveins: $q0
1212
; CHECK: [[COPY:%[0-9]+]]:qfpregs = COPY $q0
1313
; CHECK: [[COPY1:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_odd64
14-
; CHECK: [[LEAX_ADDri:%[0-9]+]]:i64regs = LEAX_ADDri %stack.0, 0
15-
; CHECK: [[ORXri:%[0-9]+]]:i64regs = ORXri killed [[LEAX_ADDri]], 8
14+
; CHECK: [[ADDri:%[0-9]+]]:i64regs = ADDri %stack.0, 0
15+
; CHECK: [[ORXri:%[0-9]+]]:i64regs = ORXri killed [[ADDri]], 8
1616
; CHECK: STDFrr [[ORXri]], $g0, killed [[COPY1]] :: (store (s64) into %stack.0 + 8)
1717
; CHECK: [[COPY2:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_even64
1818
; CHECK: STDFri %stack.0, 0, killed [[COPY2]] :: (store (s64) into %stack.0, align 16)
@@ -32,8 +32,8 @@ define fp128 @testcase(fp128 %0) {
3232
; CHECK: [[COPY7:%[0-9]+]]:i64regs = COPY [[ADDEri]]
3333
; CHECK: [[SLLXri:%[0-9]+]]:i64regs = SLLXri killed [[COPY7]], 32
3434
; CHECK: [[ORXrr:%[0-9]+]]:i64regs = ORXrr killed [[SLLXri]], killed [[SRLri]]
35-
; CHECK: [[LEAX_ADDri1:%[0-9]+]]:i64regs = LEAX_ADDri %stack.1, 0
36-
; CHECK: [[ORXri1:%[0-9]+]]:i64regs = ORXri killed [[LEAX_ADDri1]], 8
35+
; CHECK: [[ADDri1:%[0-9]+]]:i64regs = ADDri %stack.1, 0
36+
; CHECK: [[ORXri1:%[0-9]+]]:i64regs = ORXri killed [[ADDri1]], 8
3737
; CHECK: STXrr [[ORXri1]], $g0, killed [[ORXrr]] :: (store (s64) into %stack.1 + 8, basealign 16)
3838
; CHECK: [[SRLri1:%[0-9]+]]:i64regs = SRLri killed [[ADDEri1]], 0
3939
; CHECK: [[COPY8:%[0-9]+]]:i64regs = COPY [[ADDEri2]]

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