Skip to content

Commit ddb87e0

Browse files
authored
SystemZ: Use REG_SEQUENCE for PAIR128 (#90640)
PAIR128 should probably just be removed entirely Depends #90638
1 parent 58bad28 commit ddb87e0

File tree

2 files changed

+13
-21
lines changed

2 files changed

+13
-21
lines changed

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 6 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -8868,23 +8868,15 @@ SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI,
88688868
MachineBasicBlock *
88698869
SystemZTargetLowering::emitPair128(MachineInstr &MI,
88708870
MachineBasicBlock *MBB) const {
8871-
MachineFunction &MF = *MBB->getParent();
88728871
const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
8873-
MachineRegisterInfo &MRI = MF.getRegInfo();
8874-
DebugLoc DL = MI.getDebugLoc();
8872+
const DebugLoc &DL = MI.getDebugLoc();
88758873

88768874
Register Dest = MI.getOperand(0).getReg();
8877-
Register Hi = MI.getOperand(1).getReg();
8878-
Register Lo = MI.getOperand(2).getReg();
8879-
Register Tmp1 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
8880-
Register Tmp2 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
8881-
8882-
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Tmp1);
8883-
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Tmp2)
8884-
.addReg(Tmp1).addReg(Hi).addImm(SystemZ::subreg_h64);
8885-
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
8886-
.addReg(Tmp2).addReg(Lo).addImm(SystemZ::subreg_l64);
8887-
8875+
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest)
8876+
.add(MI.getOperand(1))
8877+
.addImm(SystemZ::subreg_h64)
8878+
.add(MI.getOperand(2))
8879+
.addImm(SystemZ::subreg_l64);
88888880
MI.eraseFromParent();
88898881
return MBB;
88908882
}

llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -372,8 +372,8 @@ define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) {
372372
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
373373
; CHECK-NEXT: vlgvg %r1, %v3, 1
374374
; CHECK-NEXT: vlgvg %r0, %v3, 0
375-
; CHECK-NEXT: vlgvg %r5, %v4, 1
376-
; CHECK-NEXT: vlgvg %r4, %v4, 0
375+
; CHECK-NEXT: vlgvg %r5, %v5, 1
376+
; CHECK-NEXT: vlgvg %r4, %v5, 0
377377
; CHECK-NEXT: cdsg %r0, %r4, 0(%r3)
378378
; CHECK-NEXT: vlvgp %v3, %r0, %r1
379379
; CHECK-NEXT: je .LBB12_8
@@ -386,19 +386,19 @@ define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) {
386386
; CHECK-NEXT: vchlgs %v4, %v3, %v0
387387
; CHECK-NEXT: .LBB12_4: # %atomicrmw.start
388388
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
389-
; CHECK-NEXT: vlr %v5, %v0
389+
; CHECK-NEXT: vlr %v4, %v0
390390
; CHECK-NEXT: jl .LBB12_6
391391
; CHECK-NEXT: # %bb.5: # %atomicrmw.start
392392
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
393-
; CHECK-NEXT: vaq %v5, %v3, %v1
393+
; CHECK-NEXT: vaq %v4, %v3, %v1
394394
; CHECK-NEXT: .LBB12_6: # %atomicrmw.start
395395
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
396-
; CHECK-NEXT: vceqgs %v4, %v3, %v2
397-
; CHECK-NEXT: vlr %v4, %v0
396+
; CHECK-NEXT: vceqgs %v5, %v3, %v2
397+
; CHECK-NEXT: vlr %v5, %v0
398398
; CHECK-NEXT: je .LBB12_1
399399
; CHECK-NEXT: # %bb.7: # %atomicrmw.start
400400
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
401-
; CHECK-NEXT: vlr %v4, %v5
401+
; CHECK-NEXT: vlr %v5, %v4
402402
; CHECK-NEXT: j .LBB12_1
403403
; CHECK-NEXT: .LBB12_8: # %atomicrmw.end
404404
; CHECK-NEXT: vst %v3, 0(%r2), 3

0 commit comments

Comments
 (0)