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[SPARC][IAS] Properly set implied feature sets for ISA levels/extensions (#143232)
Some SPARC ISA levels and/or extensions are defined in a way such that the availability of it implies the availability of other, more fundamental ISA features (for example, targeting 64-bit environment implies that V9 instructions are available). Properly set those in the TableGen definitions. Fixes #142388.
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‎llvm/lib/Target/Sparc/Sparc.td

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -42,22 +42,28 @@ def FeatureV8Deprecated
4242
"Enable deprecated V8 instructions in V9 mode">;
4343
def FeatureVIS
4444
: SubtargetFeature<"vis", "IsVIS", "true",
45-
"Enable UltraSPARC Visual Instruction Set extensions">;
45+
"Enable UltraSPARC Visual Instruction Set extensions",
46+
[FeatureV9]>;
4647
def FeatureVIS2
4748
: SubtargetFeature<"vis2", "IsVIS2", "true",
48-
"Enable Visual Instruction Set extensions II">;
49+
"Enable Visual Instruction Set extensions II",
50+
[FeatureV9]>;
4951
def FeatureVIS3
5052
: SubtargetFeature<"vis3", "IsVIS3", "true",
51-
"Enable Visual Instruction Set extensions III">;
53+
"Enable Visual Instruction Set extensions III",
54+
[FeatureV9]>;
5255
def FeatureUA2005
5356
: SubtargetFeature<"ua2005", "IsUA2005", "true",
54-
"Enable UltraSPARC Architecture 2005 extensions">;
57+
"Enable UltraSPARC Architecture 2005 extensions",
58+
[FeatureV9, FeatureVIS, FeatureVIS2]>;
5559
def FeatureUA2007
5660
: SubtargetFeature<"ua2007", "IsUA2007", "true",
57-
"Enable UltraSPARC Architecture 2007 extensions">;
61+
"Enable UltraSPARC Architecture 2007 extensions",
62+
[FeatureV9, FeatureVIS, FeatureVIS2]>;
5863
def FeatureOSA2011
5964
: SubtargetFeature<"osa2011", "IsOSA2011", "true",
60-
"Enable Oracle SPARC Architecture 2011 extensions">;
65+
"Enable Oracle SPARC Architecture 2011 extensions",
66+
[FeatureV9, FeatureVIS, FeatureVIS2, FeatureVIS3]>;
6167
def FeatureLeon
6268
: SubtargetFeature<"leon", "IsLeon", "true",
6369
"Enable LEON extensions">;

‎llvm/lib/Target/Sparc/SparcInstrInfo.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,8 @@ include "SparcInstrFormats.td"
2424
def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
2525

2626
// True when generating 64-bit code. This also implies HasV9.
27-
def Is64Bit : Predicate<"Subtarget->is64Bit()">;
27+
def Is64Bit : Predicate<"Subtarget->is64Bit()">,
28+
AssemblerPredicate<(all_of FeatureV9)>;
2829

2930
def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">,
3031
AssemblerPredicate<(all_of FeatureSoftMulDiv)>;

‎llvm/test/CodeGen/SPARC/ctlz.ll

Lines changed: 16 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -207,20 +207,15 @@ define i64 @i64_nopoison(i64 %x) nounwind {
207207
;
208208
; SPARC-VIS3-LABEL: i64_nopoison:
209209
; SPARC-VIS3: ! %bb.0:
210+
; SPARC-VIS3-NEXT: srl %o0, 0, %o2
211+
; SPARC-VIS3-NEXT: lzcnt %o2, %o2
212+
; SPARC-VIS3-NEXT: add %o2, -32, %o2
213+
; SPARC-VIS3-NEXT: srl %o1, 0, %o1
214+
; SPARC-VIS3-NEXT: lzcnt %o1, %o1
215+
; SPARC-VIS3-NEXT: add %o1, -32, %o1
216+
; SPARC-VIS3-NEXT: add %o1, 32, %o1
210217
; SPARC-VIS3-NEXT: cmp %o0, 0
211-
; SPARC-VIS3-NEXT: bne .LBB2_2
212-
; SPARC-VIS3-NEXT: nop
213-
; SPARC-VIS3-NEXT: ! %bb.1:
214-
; SPARC-VIS3-NEXT: srl %o1, 0, %o0
215-
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
216-
; SPARC-VIS3-NEXT: add %o0, -32, %o0
217-
; SPARC-VIS3-NEXT: add %o0, 32, %o1
218-
; SPARC-VIS3-NEXT: retl
219-
; SPARC-VIS3-NEXT: mov %g0, %o0
220-
; SPARC-VIS3-NEXT: .LBB2_2:
221-
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
222-
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
223-
; SPARC-VIS3-NEXT: add %o0, -32, %o1
218+
; SPARC-VIS3-NEXT: movne %icc, %o2, %o1
224219
; SPARC-VIS3-NEXT: retl
225220
; SPARC-VIS3-NEXT: mov %g0, %o0
226221
;
@@ -311,20 +306,15 @@ define i64 @i64_poison(i64 %x) nounwind {
311306
;
312307
; SPARC-VIS3-LABEL: i64_poison:
313308
; SPARC-VIS3: ! %bb.0:
309+
; SPARC-VIS3-NEXT: srl %o0, 0, %o2
310+
; SPARC-VIS3-NEXT: lzcnt %o2, %o2
311+
; SPARC-VIS3-NEXT: add %o2, -32, %o2
312+
; SPARC-VIS3-NEXT: srl %o1, 0, %o1
313+
; SPARC-VIS3-NEXT: lzcnt %o1, %o1
314+
; SPARC-VIS3-NEXT: add %o1, -32, %o1
315+
; SPARC-VIS3-NEXT: add %o1, 32, %o1
314316
; SPARC-VIS3-NEXT: cmp %o0, 0
315-
; SPARC-VIS3-NEXT: bne .LBB3_2
316-
; SPARC-VIS3-NEXT: nop
317-
; SPARC-VIS3-NEXT: ! %bb.1:
318-
; SPARC-VIS3-NEXT: srl %o1, 0, %o0
319-
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
320-
; SPARC-VIS3-NEXT: add %o0, -32, %o0
321-
; SPARC-VIS3-NEXT: add %o0, 32, %o1
322-
; SPARC-VIS3-NEXT: retl
323-
; SPARC-VIS3-NEXT: mov %g0, %o0
324-
; SPARC-VIS3-NEXT: .LBB3_2:
325-
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
326-
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
327-
; SPARC-VIS3-NEXT: add %o0, -32, %o1
317+
; SPARC-VIS3-NEXT: movne %icc, %o2, %o1
328318
; SPARC-VIS3-NEXT: retl
329319
; SPARC-VIS3-NEXT: mov %g0, %o0
330320
;

‎llvm/test/CodeGen/SPARC/cttz.ll

Lines changed: 20 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -254,28 +254,25 @@ define i64 @i64_nopoison(i64 %x) nounwind {
254254
;
255255
; SPARC-VIS3-LABEL: i64_nopoison:
256256
; SPARC-VIS3: ! %bb.0:
257-
; SPARC-VIS3-NEXT: cmp %o1, 0
258-
; SPARC-VIS3-NEXT: bne .LBB2_2
259-
; SPARC-VIS3-NEXT: nop
260-
; SPARC-VIS3-NEXT: ! %bb.1:
261-
; SPARC-VIS3-NEXT: add %o0, -1, %o1
262-
; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
257+
; SPARC-VIS3-NEXT: add %o0, -1, %o2
258+
; SPARC-VIS3-NEXT: andn %o2, %o0, %o0
263259
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
264260
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
265261
; SPARC-VIS3-NEXT: add %o0, -32, %o0
266-
; SPARC-VIS3-NEXT: ba .LBB2_3
267-
; SPARC-VIS3-NEXT: mov 64, %o1
268-
; SPARC-VIS3-NEXT: .LBB2_2:
262+
; SPARC-VIS3-NEXT: mov 64, %o2
263+
; SPARC-VIS3-NEXT: sub %o2, %o0, %o2
269264
; SPARC-VIS3-NEXT: add %o1, -1, %o0
270265
; SPARC-VIS3-NEXT: andn %o0, %o1, %o0
271266
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
272267
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
273268
; SPARC-VIS3-NEXT: add %o0, -32, %o0
274-
; SPARC-VIS3-NEXT: mov 32, %o1
275-
; SPARC-VIS3-NEXT: .LBB2_3:
276-
; SPARC-VIS3-NEXT: sub %o1, %o0, %o1
277-
; SPARC-VIS3-NEXT: retl
269+
; SPARC-VIS3-NEXT: mov 32, %o3
270+
; SPARC-VIS3-NEXT: sub %o3, %o0, %o0
271+
; SPARC-VIS3-NEXT: cmp %o1, 0
272+
; SPARC-VIS3-NEXT: movne %icc, %o0, %o2
278273
; SPARC-VIS3-NEXT: mov %g0, %o0
274+
; SPARC-VIS3-NEXT: retl
275+
; SPARC-VIS3-NEXT: mov %o2, %o1
279276
;
280277
; SPARC64-LABEL: i64_nopoison:
281278
; SPARC64: ! %bb.0:
@@ -376,28 +373,25 @@ define i64 @i64_poison(i64 %x) nounwind {
376373
;
377374
; SPARC-VIS3-LABEL: i64_poison:
378375
; SPARC-VIS3: ! %bb.0:
379-
; SPARC-VIS3-NEXT: cmp %o1, 0
380-
; SPARC-VIS3-NEXT: bne .LBB3_2
381-
; SPARC-VIS3-NEXT: nop
382-
; SPARC-VIS3-NEXT: ! %bb.1:
383-
; SPARC-VIS3-NEXT: add %o0, -1, %o1
384-
; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
376+
; SPARC-VIS3-NEXT: add %o0, -1, %o2
377+
; SPARC-VIS3-NEXT: andn %o2, %o0, %o0
385378
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
386379
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
387380
; SPARC-VIS3-NEXT: add %o0, -32, %o0
388-
; SPARC-VIS3-NEXT: ba .LBB3_3
389-
; SPARC-VIS3-NEXT: mov 64, %o1
390-
; SPARC-VIS3-NEXT: .LBB3_2:
381+
; SPARC-VIS3-NEXT: mov 64, %o2
382+
; SPARC-VIS3-NEXT: sub %o2, %o0, %o2
391383
; SPARC-VIS3-NEXT: add %o1, -1, %o0
392384
; SPARC-VIS3-NEXT: andn %o0, %o1, %o0
393385
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
394386
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
395387
; SPARC-VIS3-NEXT: add %o0, -32, %o0
396-
; SPARC-VIS3-NEXT: mov 32, %o1
397-
; SPARC-VIS3-NEXT: .LBB3_3:
398-
; SPARC-VIS3-NEXT: sub %o1, %o0, %o1
399-
; SPARC-VIS3-NEXT: retl
388+
; SPARC-VIS3-NEXT: mov 32, %o3
389+
; SPARC-VIS3-NEXT: sub %o3, %o0, %o0
390+
; SPARC-VIS3-NEXT: cmp %o1, 0
391+
; SPARC-VIS3-NEXT: movne %icc, %o0, %o2
400392
; SPARC-VIS3-NEXT: mov %g0, %o0
393+
; SPARC-VIS3-NEXT: retl
394+
; SPARC-VIS3-NEXT: mov %o2, %o1
401395
;
402396
; SPARC64-LABEL: i64_poison:
403397
; SPARC64: ! %bb.0:

‎llvm/test/CodeGen/SPARC/inlineasm-v9.ll

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,3 +58,12 @@ Entry:
5858
tail call void asm sideeffect "", "{o0}"(i64 %val)
5959
ret void
6060
}
61+
62+
; CHECK-LABEL: test_twinword:
63+
; CHECK: rd %pc, %i1
64+
; CHECK: srlx %i1, 32, %i0
65+
66+
define i64 @test_twinword(){
67+
%1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i0}"()
68+
ret i64 %1
69+
}

‎llvm/test/CodeGen/SPARC/inlineasm.ll

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -144,15 +144,6 @@ entry:
144144
ret void
145145
}
146146

147-
; CHECK-LABEL: test_twinword:
148-
; CHECK: rd %asr5, %i1
149-
; CHECK: srlx %i1, 32, %i0
150-
151-
define i64 @test_twinword(){
152-
%1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i0}"()
153-
ret i64 %1
154-
}
155-
156147
; CHECK-LABEL: test_symbol:
157148
; CHECK: ba,a brtarget
158149
define void @test_symbol() {

‎llvm/test/MC/Sparc/Relocations/relocation-specifier.s

Lines changed: 41 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,21 @@
11
# RUN: llvm-mc %s -triple=sparc | FileCheck %s --check-prefix=ASM
2-
# RUN: llvm-mc %s -triple=sparcv9 | FileCheck %s --check-prefix=ASM
2+
# RUN: llvm-mc %s --defsym V9=1 -triple=sparcv9 | FileCheck %s --check-prefixes=ASM,ASM-V9
33

44
# RUN: llvm-mc %s -triple=sparc -filetype=obj -o %t
55
# RUN: llvm-objdump -dr %t | FileCheck %s --check-prefix=OBJDUMP
6-
# RUN: llvm-mc %s -triple=sparcv9 -filetype=obj -o %t
7-
# RUN: llvm-objdump -dr %t | FileCheck %s --check-prefix=OBJDUMP
86
# RUN: llvm-readelf -s - < %t | FileCheck %s --check-prefix=READELF --implicit-check-not=TLS
7+
# RUN: llvm-mc %s --defsym V9=1 -triple=sparcv9 -filetype=obj -o %t
8+
# RUN: llvm-objdump -dr %t | FileCheck %s --check-prefixes=OBJDUMP,OBJDUMP-V9
9+
# RUN: llvm-readelf -s - < %t | FileCheck %s --check-prefixes=READELF,READELF-V9 --implicit-check-not=TLS
910

1011
# READELF: TLS LOCAL DEFAULT [[#]] s_tle_hix22
1112
# READELF: TLS LOCAL DEFAULT [[#]] s_tldo_hix22
1213
# READELF: TLS GLOBAL DEFAULT UND s_tle_lox10
13-
# READELF: TLS GLOBAL DEFAULT UND s_tie_hi22
14-
# READELF: TLS GLOBAL DEFAULT UND s_tie_lo10
15-
# READELF: TLS GLOBAL DEFAULT UND s_tie_ld
16-
# READELF: TLS GLOBAL DEFAULT UND s_tie_ldx
17-
# READELF: TLS GLOBAL DEFAULT UND s_tie_add
14+
# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_hi22
15+
# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_lo10
16+
# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_ld
17+
# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_ldx
18+
# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_add
1819
# READELF: TLS GLOBAL DEFAULT UND s_tldm_hi22
1920
# READELF: TLS GLOBAL DEFAULT UND s_tldm_lo10
2021
# READELF: TLS GLOBAL DEFAULT UND s_tldm_add
@@ -72,30 +73,32 @@ or %g1, %hm(sym), %g3
7273
or %g1, %ulo(sym), %g3
7374
sethi %lm(sym), %l0
7475

75-
# ASM: sethi %hix(sym), %g1
76-
# ASM-NEXT: xor %g1, %lox(sym), %g1
77-
# ASM-NEXT: sethi %gdop_hix22(sym), %l1
78-
# ASM-NEXT: or %l1, %gdop_lox10(sym), %l1
79-
# ASM-NEXT: ldx [%l7+%l1], %l2, %gdop(sym)
80-
# OBJDUMP: sethi 0x3fffff, %g0
81-
# OBJDUMP-NEXT: xor %g0, -0x400, %g0
82-
# OBJDUMP-NEXT: sethi 0x0, %g1
83-
# OBJDUMP-NEXT: R_SPARC_HIX22 sym
84-
# OBJDUMP-NEXT: xor %g1, 0x0, %g1
85-
# OBJDUMP-NEXT: R_SPARC_LOX10 sym
86-
# OBJDUMP-NEXT: sethi 0x0, %l1
87-
# OBJDUMP-NEXT: R_SPARC_GOTDATA_OP_HIX22 sym
88-
# OBJDUMP-NEXT: or %l1, 0x0, %l1
89-
# OBJDUMP-NEXT: R_SPARC_GOTDATA_OP_LOX10 sym
90-
# OBJDUMP-NEXT: ldx [%l7+%l1], %l2
91-
# OBJDUMP-NEXT: R_SPARC_GOTDATA_OP sym
76+
.ifdef V9
77+
# ASM-V9: sethi %hix(sym), %g1
78+
# ASM-V9-NEXT: xor %g1, %lox(sym), %g1
79+
# ASM-V9-NEXT: sethi %gdop_hix22(sym), %l1
80+
# ASM-V9-NEXT: or %l1, %gdop_lox10(sym), %l1
81+
# ASM-V9-NEXT: ldx [%l7+%l1], %l2, %gdop(sym)
82+
# OBJDUMP-V9: sethi 0x3fffff, %g0
83+
# OBJDUMP-V9-NEXT: xor %g0, -0x400, %g0
84+
# OBJDUMP-V9-NEXT: sethi 0x0, %g1
85+
# OBJDUMP-V9-NEXT: R_SPARC_HIX22 sym
86+
# OBJDUMP-V9-NEXT: xor %g1, 0x0, %g1
87+
# OBJDUMP-V9-NEXT: R_SPARC_LOX10 sym
88+
# OBJDUMP-V9-NEXT: sethi 0x0, %l1
89+
# OBJDUMP-V9-NEXT: R_SPARC_GOTDATA_OP_HIX22 sym
90+
# OBJDUMP-V9-NEXT: or %l1, 0x0, %l1
91+
# OBJDUMP-V9-NEXT: R_SPARC_GOTDATA_OP_LOX10 sym
92+
# OBJDUMP-V9-NEXT: ldx [%l7+%l1], %l2
93+
# OBJDUMP-V9-NEXT: R_SPARC_GOTDATA_OP sym
9294
sethi %hix(zero), %g0
9395
xor %g0, %lox(zero), %g0
9496
sethi %hix(sym), %g1
9597
xor %g1, %lox(sym), %g1
9698
sethi %gdop_hix22(sym), %l1
9799
or %l1, %gdop_lox10(sym), %l1
98100
ldx [%l7 + %l1], %l2, %gdop(sym)
101+
.endif
99102

100103
.set abs, 0xfedcba98
101104
.set abs48, 0xfedcba987654
@@ -147,23 +150,25 @@ xor %o0, %lox(abs), %o0
147150
sethi %tle_hix22(s_tle_hix22), %i0
148151
xor %i0, %tle_lox10(s_tle_lox10), %i0
149152

153+
.ifdef V9
150154
## Initial Executable model
151-
# ASM: sethi %tie_hi22(s_tie_hi22), %i1
152-
# ASM-NEXT: add %i1, %tie_lo10(s_tie_lo10), %i1
153-
# ASM-NEXT: ld [%i0+%i1], %i0, %tie_ld(s_tie_ld)
154-
# ASM-NEXT: ldx [%i0+%i1], %i0, %tie_ldx(s_tie_ldx)
155-
# ASM-NEXT: add %g7, %i0, %o0, %tie_add(s_tie_add)
156-
157-
# OBJDUMP: R_SPARC_TLS_IE_HI22 s_tie_hi22
158-
# OBJDUMP: R_SPARC_TLS_IE_LO10 s_tie_lo10
159-
# OBJDUMP: R_SPARC_TLS_IE_LD s_tie_ld
160-
# OBJDUMP: R_SPARC_TLS_IE_LDX s_tie_ldx
161-
# OBJDUMP: R_SPARC_TLS_IE_ADD s_tie_add
155+
# ASM-V9: sethi %tie_hi22(s_tie_hi22), %i1
156+
# ASM-V9-NEXT: add %i1, %tie_lo10(s_tie_lo10), %i1
157+
# ASM-V9-NEXT: ld [%i0+%i1], %i0, %tie_ld(s_tie_ld)
158+
# ASM-V9-NEXT: ldx [%i0+%i1], %i0, %tie_ldx(s_tie_ldx)
159+
# ASM-V9-NEXT: add %g7, %i0, %o0, %tie_add(s_tie_add)
160+
161+
# OBJDUMP-V9: R_SPARC_TLS_IE_HI22 s_tie_hi22
162+
# OBJDUMP-V9: R_SPARC_TLS_IE_LO10 s_tie_lo10
163+
# OBJDUMP-V9: R_SPARC_TLS_IE_LD s_tie_ld
164+
# OBJDUMP-V9: R_SPARC_TLS_IE_LDX s_tie_ldx
165+
# OBJDUMP-V9: R_SPARC_TLS_IE_ADD s_tie_add
162166
sethi %tie_hi22(s_tie_hi22), %i1
163167
add %i1, %tie_lo10(s_tie_lo10), %i1
164168
ld [%i0+%i1], %i0, %tie_ld(s_tie_ld)
165169
ldx [%i0+%i1], %i0, %tie_ldx(s_tie_ldx)
166170
add %g7, %i0, %o0, %tie_add(s_tie_add)
171+
.endif
167172

168173
## Local Dynamic model
169174
# ASM: sethi %tldo_hix22(s_tldo_hix22), %i1

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