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[AMDGPU][AsmParser][NFC] Simplify v_interp-related operand definitions.
Part of <#62629>. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D152897
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6 files changed

+24
-46
lines changed

6 files changed

+24
-46
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,7 @@ class CustomOperandProps<bit optional = 0, string name = NAME> {
150150
class CustomOperand<ValueType type, bit optional = 0, string name = NAME>
151151
: Operand<type>, CustomOperandProps<optional, name>;
152152

153-
class ImmOperand<ValueType type, string name, bit optional = 0,
153+
class ImmOperand<ValueType type, string name = NAME, bit optional = 0,
154154
string printer = "print"#name>
155155
: CustomOperand<type, optional, name> {
156156
let ImmTy = "ImmTyNone";

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
146146
ImmTySendMsg,
147147
ImmTyInterpSlot,
148148
ImmTyInterpAttr,
149-
ImmTyAttrChan,
149+
ImmTyInterpAttrChan,
150150
ImmTyOpSel,
151151
ImmTyOpSelHi,
152152
ImmTyNegLo,
@@ -392,7 +392,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
392392
bool isSDWADstUnused() const { return isImmTy(ImmTySDWADstUnused); }
393393
bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }
394394
bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }
395-
bool isAttrChan() const { return isImmTy(ImmTyAttrChan); }
395+
bool isInterpAttrChan() const { return isImmTy(ImmTyInterpAttrChan); }
396396
bool isOpSel() const { return isImmTy(ImmTyOpSel); }
397397
bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
398398
bool isNegLo() const { return isImmTy(ImmTyNegLo); }
@@ -1068,7 +1068,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
10681068
case ImmTySendMsg: OS << "SendMsg"; break;
10691069
case ImmTyInterpSlot: OS << "InterpSlot"; break;
10701070
case ImmTyInterpAttr: OS << "InterpAttr"; break;
1071-
case ImmTyAttrChan: OS << "AttrChan"; break;
1071+
case ImmTyInterpAttrChan: OS << "InterpAttrChan"; break;
10721072
case ImmTyOpSel: OS << "OpSel"; break;
10731073
case ImmTyOpSelHi: OS << "OpSelHi"; break;
10741074
case ImmTyNegLo: OS << "NegLo"; break;
@@ -7075,8 +7075,8 @@ OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
70757075

70767076
Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,
70777077
AMDGPUOperand::ImmTyInterpAttr));
7078-
Operands.push_back(AMDGPUOperand::CreateImm(this, AttrChan, SChan,
7079-
AMDGPUOperand::ImmTyAttrChan));
7078+
Operands.push_back(AMDGPUOperand::CreateImm(
7079+
this, AttrChan, SChan, AMDGPUOperand::ImmTyInterpAttrChan));
70807080
return MatchOperand_Success;
70817081
}
70827082

@@ -8090,9 +8090,8 @@ void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
80908090
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
80918091
if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
80928092
Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
8093-
} else if (Op.isInterpSlot() ||
8094-
Op.isInterpAttr() ||
8095-
Op.isAttrChan()) {
8093+
} else if (Op.isInterpSlot() || Op.isInterpAttr() ||
8094+
Op.isInterpAttrChan()) {
80968095
Inst.addOperand(MCOperand::createImm(Op.getImm()));
80978096
} else if (Op.isImmModifier()) {
80988097
OptionalIdx[Op.getImmTy()] = I;
@@ -9100,10 +9099,10 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
91009099
return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;
91019100
case MCK_InterpSlot:
91029101
return Operand.isInterpSlot() ? Match_Success : Match_InvalidOperand;
9103-
case MCK_Attr:
9102+
case MCK_InterpAttr:
91049103
return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;
9105-
case MCK_AttrChan:
9106-
return Operand.isAttrChan() ? Match_Success : Match_InvalidOperand;
9104+
case MCK_InterpAttrChan:
9105+
return Operand.isInterpAttrChan() ? Match_Success : Match_InvalidOperand;
91079106
case MCK_SReg_64:
91089107
case MCK_SReg_64_XEXEC:
91099108
// Null is defined as a 32-bit register but

‎llvm/lib/Target/AMDGPU/LDSDIRInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ class LDSDIRe<bits<2> op, bit is_direct> : Enc32 {
3434
class LDSDIR_getIns<bit direct> {
3535
dag ret = !if(direct,
3636
(ins wait_vdst:$waitvdst),
37-
(ins Attr:$attr, AttrChan:$attrchan, wait_vdst:$waitvdst)
37+
(ins InterpAttr:$attr, InterpAttrChan:$attrchan, wait_vdst:$waitvdst)
3838
);
3939
}
4040

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 3 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -935,35 +935,13 @@ def sopp_brtarget : Operand<OtherVT> {
935935

936936
def si_ga : Operand<iPTR>;
937937

938-
def InterpSlotMatchClass : AsmOperandClass {
939-
let Name = "InterpSlot";
940-
let PredicateMethod = "isInterpSlot";
941-
let ParserMethod = "parseInterpSlot";
942-
let RenderMethod = "addImmOperands";
943-
}
944-
945-
def InterpSlot : Operand<i32> {
946-
let PrintMethod = "printInterpSlot";
947-
let ParserMatchClass = InterpSlotMatchClass;
948-
let OperandType = "OPERAND_IMMEDIATE";
949-
}
950-
951-
def AttrMatchClass : AsmOperandClass {
952-
let Name = "Attr";
953-
let PredicateMethod = "isInterpAttr";
954-
let ParserMethod = "parseInterpAttr";
955-
let RenderMethod = "addImmOperands";
956-
}
938+
def InterpSlot : CustomOperand<i32>;
957939

958940
// It appears to be necessary to create a separate operand for this to
959941
// be able to parse attr<num> with no space.
960-
def Attr : Operand<i32> {
961-
let PrintMethod = "printInterpAttr";
962-
let ParserMatchClass = AttrMatchClass;
963-
let OperandType = "OPERAND_IMMEDIATE";
964-
}
942+
def InterpAttr : CustomOperand<i32>;
965943

966-
def AttrChan : ImmOperand<i32, "AttrChan", 0, "printInterpAttrChan">;
944+
def InterpAttrChan : ImmOperand<i32>;
967945

968946
def SendMsgMatchClass : AsmOperandClass {
969947
let Name = "SendMsg";

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ let Uses = [MODE, M0, EXEC] in {
4747
multiclass V_INTERP_P1_F32_m : VINTRP_m <
4848
0x00000000,
4949
(outs VINTRPDst:$vdst),
50-
(ins VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
50+
(ins VGPR_32:$vsrc, InterpAttr:$attr, InterpAttrChan:$attrchan),
5151
"v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",
5252
[(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
5353
(i32 timm:$attrchan), (i32 timm:$attr), M0))]
@@ -73,7 +73,8 @@ let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
7373
defm V_INTERP_P2_F32 : VINTRP_m <
7474
0x00000001,
7575
(outs VINTRPDst:$vdst),
76-
(ins VGPR_32:$src0, VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
76+
(ins VGPR_32:$src0, VGPR_32:$vsrc, InterpAttr:$attr,
77+
InterpAttrChan:$attrchan),
7778
"v_interp_p2_f32$vdst, $vsrc, $attr$attrchan",
7879
[(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
7980
(i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
@@ -83,7 +84,7 @@ defm V_INTERP_P2_F32 : VINTRP_m <
8384
defm V_INTERP_MOV_F32 : VINTRP_m <
8485
0x00000002,
8586
(outs VINTRPDst:$vdst),
86-
(ins InterpSlot:$vsrc, Attr:$attr, AttrChan:$attrchan),
87+
(ins InterpSlot:$vsrc, InterpAttr:$attr, InterpAttrChan:$attrchan),
8788
"v_interp_mov_f32$vdst, $vsrc, $attr$attrchan",
8889
[(set f32:$vdst, (int_amdgcn_interp_mov (i32 timm:$vsrc),
8990
(i32 timm:$attrchan), (i32 timm:$attr), M0))]>;

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -61,15 +61,15 @@ class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> :
6161
def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
6262
let Src0Mod = FPVRegInputMods;
6363
let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
64-
Attr:$attr, AttrChan:$attrchan,
64+
InterpAttr:$attr, InterpAttrChan:$attrchan,
6565
clampmod0:$clamp, omod0:$omod);
6666

6767
let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
6868
}
6969

7070
def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
7171
let Ins64 = (ins InterpSlot:$src0,
72-
Attr:$attr, AttrChan:$attrchan,
72+
InterpAttr:$attr, InterpAttrChan:$attrchan,
7373
clampmod0:$clamp, omod0:$omod);
7474

7575
let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
@@ -90,16 +90,16 @@ class getInterp16Ins <bit HasSrc2, bit HasOMod,
9090
dag ret = !if(HasSrc2,
9191
!if(HasOMod,
9292
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
93-
Attr:$attr, AttrChan:$attrchan,
93+
InterpAttr:$attr, InterpAttrChan:$attrchan,
9494
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
9595
highmod:$high, clampmod0:$clamp, omod0:$omod),
9696
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
97-
Attr:$attr, AttrChan:$attrchan,
97+
InterpAttr:$attr, InterpAttrChan:$attrchan,
9898
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
9999
highmod:$high, clampmod0:$clamp)
100100
),
101101
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
102-
Attr:$attr, AttrChan:$attrchan,
102+
InterpAttr:$attr, InterpAttrChan:$attrchan,
103103
highmod:$high, clampmod0:$clamp, omod0:$omod)
104104
);
105105
}

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