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Thorsten Schütt
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[GlobalISel] Import extract/insert subvector
Tests are limited to fixed-length vectors. Test: AArch64/GlobalISel/irtranslator-subvector.ll Reference: https://llvm.org/docs/LangRef.html#llvm-vector-extract-intrinsic https://llvm.org/docs/LangRef.html#llvm-vector-insert-intrinsic
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‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

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@@ -2588,6 +2588,20 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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getOrCreateVReg(*CI.getOperand(0)),
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getOrCreateVReg(*CI.getOperand(1)));
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return true;
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case Intrinsic::vector_extract: {
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ConstantInt *Index = cast<ConstantInt>(CI.getOperand(1));
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MIRBuilder.buildExtractSubvector(getOrCreateVReg(CI),
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getOrCreateVReg(*CI.getOperand(0)),
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Index->getZExtValue());
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return true;
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}
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case Intrinsic::vector_insert: {
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ConstantInt *Index = cast<ConstantInt>(CI.getOperand(2));
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MIRBuilder.buildInsertSubvector(
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getOrCreateVReg(CI), getOrCreateVReg(*CI.getOperand(0)),
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getOrCreateVReg(*CI.getOperand(1)), Index->getZExtValue());
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return true;
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}
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case Intrinsic::prefetch: {
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Value *Addr = CI.getOperand(0);
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unsigned RW = cast<ConstantInt>(CI.getOperand(1))->getZExtValue();

‎llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll

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@@ -0,0 +1,78 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
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define i32 @extract_v4i32_vector_insert_const(<4 x i32> %a, <2 x i32> %b, i32 %c) {
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; CHECK-LABEL: name: extract_v4i32_vector_insert_const
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $d1, $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x s32>), 0
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; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[C]](s64)
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; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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entry:
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%vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)
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%d = extractelement <4 x i32> %vector, i32 1
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ret i32 %d
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}
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define i32 @extract_v4i32_vector_insert(<4 x i32> %a, <2 x i32> %b, i32 %c) {
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; CHECK-LABEL: name: extract_v4i32_vector_insert
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $d1, $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x s32>), 0
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[ZEXT]](s64)
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; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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entry:
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%vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)
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%d = extractelement <4 x i32> %vector, i32 %c
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ret i32 %d
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}
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define i32 @extract_v4i32_vector_extract(<4 x i32> %a, <2 x i32> %b, i32 %c) {
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; CHECK-LABEL: name: extract_v4i32_vector_extract
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $d1, $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<4 x s32>), 0
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[EXTRACT_SUBVECTOR]](<4 x s32>), [[ZEXT]](s64)
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; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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entry:
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%vector = call <4 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %a, i64 0)
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%d = extractelement <4 x i32> %vector, i32 %c
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ret i32 %d
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}
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define i32 @extract_v4i32_vector_extract_const(<4 x i32> %a, <2 x i32> %b, i32 %c) {
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; CHECK-LABEL: name: extract_v4i32_vector_extract_const
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $d1, $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<4 x s32>), 0
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; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[EXTRACT_SUBVECTOR]](<4 x s32>), [[C]](s64)
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; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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entry:
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%vector = call <4 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %a, i64 0)
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%d = extractelement <4 x i32> %vector, i32 0
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ret i32 %d
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}

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