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[AArch64] Fix postinc operands for Neoverse-N1 scheduling
Similar to D159254, this fixes the order of WriteAdr operands on post/pre-inc loads/stores in the Neoverse-N1 scheduling model.
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+2075
-2086
lines changed

2 files changed

+2075
-2086
lines changed

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td‎

Lines changed: 41 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -377,7 +377,7 @@ def : InstRW<[N1Write_4c_1L, N1Write_0c_0Z], (instrs LDPWi, LDNPWi)>;
377377
def : InstRW<[N1Write_5c_1I_1L, N1Write_0c_0Z], (instrs LDPSWi)>;
378378

379379
// Load pair, immed post or pre-index, signed words
380-
def : InstRW<[N1Write_5c_1I_1L, N1Write_0c_0Z, WriteAdr],
380+
def : InstRW<[WriteAdr, N1Write_5c_1I_1L, N1Write_0c_0Z],
381381
(instrs LDPSWpost, LDPSWpre)>;
382382

383383

@@ -477,7 +477,7 @@ def : InstRW<[N1Write_5c_1L, ReadAdrBase], (instregex "^LDR[SDQ]l$",
477477

478478
// Load vector reg, immed post-index
479479
// Load vector reg, immed pre-index
480-
def : InstRW<[N1Write_5c_1L, WriteAdr],
480+
def : InstRW<[WriteAdr, N1Write_5c_1L],
481481
(instregex "^LDR[BHSDQ](post|pre)$")>;
482482

483483
// Load vector reg, unsigned immed
@@ -501,12 +501,12 @@ def : InstRW<[N1Write_7c_1I_1L, WriteLDHi], (instregex "^LDPN?[HQ]i$")>;
501501

502502
// Load vector pair, immed post-index, S/D-form
503503
// Load vector pair, immed pre-index, S/D-form
504-
def : InstRW<[N1Write_5c_1L, WriteLDHi, WriteAdr],
504+
def : InstRW<[WriteAdr, N1Write_5c_1L, WriteLDHi],
505505
(instregex "^LDP[SD](pre|post)$")>;
506506

507507
// Load vector pair, immed post-index, Q-form
508508
// Load vector pair, immed pre-index, Q-form
509-
def : InstRW<[N1Write_7c_1L, WriteLDHi, WriteAdr],
509+
def : InstRW<[WriteAdr, N1Write_7c_1L, WriteLDHi],
510510
(instrs LDPQpost, LDPQpre)>;
511511

512512

@@ -521,11 +521,11 @@ def : InstRW<[N1Write_2c_2I_2L], (instrs STURQi)>;
521521

522522
// Store vector reg, immed post-index, B/H/S/D-form
523523
// Store vector reg, immed pre-index, B/H/S/D-form
524-
def : InstRW<[N1Write_2c_1L_1V, WriteAdr], (instregex "^STR[BHSD](pre|post)$")>;
524+
def : InstRW<[WriteAdr, N1Write_2c_1L_1V], (instregex "^STR[BHSD](pre|post)$")>;
525525

526526
// Store vector reg, immed pre-index, Q-form
527527
// Store vector reg, immed post-index, Q-form
528-
def : InstRW<[N1Write_2c_2L_2V, WriteAdr], (instrs STRQpre, STRQpost)>;
528+
def : InstRW<[WriteAdr, N1Write_2c_2L_2V], (instrs STRQpre, STRQpost)>;
529529

530530
// Store vector reg, unsigned immed, B/H/S/D-form
531531
def : InstRW<[N1Write_2c_1L_1V], (instregex "^STR[BHSD]ui$")>;
@@ -562,15 +562,15 @@ def : InstRW<[N1Write_3c_4L_2V], (instrs STPQi, STNPQi)>;
562562

563563
// Store vector pair, immed post-index, S-form
564564
// Store vector pair, immed pre-index, S-form
565-
def : InstRW<[N1Write_2c_1L_1V, WriteAdr], (instrs STPSpre, STPSpost)>;
565+
def : InstRW<[WriteAdr, N1Write_2c_1L_1V], (instrs STPSpre, STPSpost)>;
566566

567567
// Store vector pair, immed post-index, D-form
568568
// Store vector pair, immed pre-index, D-form
569-
def : InstRW<[N1Write_2c_2L_2V, WriteAdr], (instrs STPDpre, STPDpost)>;
569+
def : InstRW<[WriteAdr, N1Write_2c_2L_2V], (instrs STPDpre, STPDpost)>;
570570

571571
// Store vector pair, immed post-index, Q-form
572572
// Store vector pair, immed pre-index, Q-form
573-
def : InstRW<[N1Write_3c_4L_2V, WriteAdr], (instrs STPQpre, STPQpost)>;
573+
def : InstRW<[WriteAdr, N1Write_3c_4L_2V], (instrs STPQpre, STPQpost)>;
574574

575575

576576
// ASIMD integer instructions
@@ -818,33 +818,33 @@ def : InstRW<[N1Write_5c_1M_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;
818818
// ASIMD load, 1 element, multiple, 1 reg
819819
def : InstRW<[N1Write_5c_1L],
820820
(instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
821-
def : InstRW<[N1Write_5c_1L, WriteAdr],
821+
def : InstRW<[WriteAdr, N1Write_5c_1L],
822822
(instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
823823

824824
// ASIMD load, 1 element, multiple, 2 reg
825825
def : InstRW<[N1Write_5c_2L],
826826
(instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
827-
def : InstRW<[N1Write_5c_2L, WriteAdr],
827+
def : InstRW<[WriteAdr, N1Write_5c_2L],
828828
(instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
829829

830830
// ASIMD load, 1 element, multiple, 3 reg
831831
def : InstRW<[N1Write_6c_3L],
832832
(instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
833-
def : InstRW<[N1Write_6c_3L, WriteAdr],
833+
def : InstRW<[WriteAdr, N1Write_6c_3L],
834834
(instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
835835

836836
// ASIMD load, 1 element, multiple, 4 reg
837837
def : InstRW<[N1Write_6c_4L],
838838
(instregex "^LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
839-
def : InstRW<[N1Write_6c_4L, WriteAdr],
839+
def : InstRW<[WriteAdr, N1Write_6c_4L],
840840
(instregex "^LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
841841

842842
// ASIMD load, 1 element, one lane
843843
// ASIMD load, 1 element, all lanes
844844
def : InstRW<[N1Write_7c_1L_1V],
845845
(instregex "LD1(i|Rv)(8|16|32|64)$",
846846
"LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
847-
def : InstRW<[N1Write_7c_1L_1V, WriteAdr],
847+
def : InstRW<[WriteAdr, N1Write_7c_1L_1V],
848848
(instregex "LD1i(8|16|32|64)_POST$",
849849
"LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
850850

@@ -855,44 +855,44 @@ def : InstRW<[N1Write_7c_2L_2V],
855855
(instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)$",
856856
"LD2i(8|16|32|64)$",
857857
"LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
858-
def : InstRW<[N1Write_7c_2L_2V, WriteAdr],
858+
def : InstRW<[WriteAdr, N1Write_7c_2L_2V],
859859
(instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)_POST$",
860860
"LD2i(8|16|32|64)_POST$",
861861
"LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
862862

863863
// ASIMD load, 3 element, multiple
864864
def : InstRW<[N1Write_8c_3L_3V],
865865
(instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)$")>;
866-
def : InstRW<[N1Write_8c_3L_3V, WriteAdr],
866+
def : InstRW<[WriteAdr, N1Write_8c_3L_3V],
867867
(instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
868868

869869
// ASIMD load, 3 element, one lane
870870
// ASIMD load, 3 element, all lanes
871871
def : InstRW<[N1Write_7c_2L_3V],
872872
(instregex "LD3i(8|16|32|64)$",
873873
"LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
874-
def : InstRW<[N1Write_7c_2L_3V, WriteAdr],
874+
def : InstRW<[WriteAdr, N1Write_7c_2L_3V],
875875
(instregex "LD3i(8|16|32|64)_POST$",
876876
"LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
877877

878878
// ASIMD load, 4 element, multiple, D-form
879879
def : InstRW<[N1Write_8c_3L_4V],
880880
(instregex "LD4Fourv(8b|4h|2s)$")>;
881-
def : InstRW<[N1Write_8c_3L_4V, WriteAdr],
881+
def : InstRW<[WriteAdr, N1Write_8c_3L_4V],
882882
(instregex "LD4Fourv(8b|4h|2s)_POST$")>;
883883

884884
// ASIMD load, 4 element, multiple, Q-form
885885
def : InstRW<[N1Write_10c_4L_4V],
886886
(instregex "LD4Fourv(16b|8h|4s|2d)$")>;
887-
def : InstRW<[N1Write_10c_4L_4V, WriteAdr],
887+
def : InstRW<[WriteAdr, N1Write_10c_4L_4V],
888888
(instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
889889

890890
// ASIMD load, 4 element, one lane
891891
// ASIMD load, 4 element, all lanes
892892
def : InstRW<[N1Write_8c_4L_4V],
893893
(instregex "LD4i(8|16|32|64)$",
894894
"LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
895-
def : InstRW<[N1Write_8c_4L_4V, WriteAdr],
895+
def : InstRW<[WriteAdr, N1Write_8c_4L_4V],
896896
(instregex "LD4i(8|16|32|64)_POST$",
897897
"LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
898898

@@ -903,127 +903,127 @@ def : InstRW<[N1Write_8c_4L_4V, WriteAdr],
903903
// ASIMD store, 1 element, multiple, 1 reg, D-form
904904
def : InstRW<[N1Write_2c_1L_1V],
905905
(instregex "ST1Onev(8b|4h|2s|1d)$")>;
906-
def : InstRW<[N1Write_2c_1L_1V, WriteAdr],
906+
def : InstRW<[WriteAdr, N1Write_2c_1L_1V],
907907
(instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
908908

909909
// ASIMD store, 1 element, multiple, 1 reg, Q-form
910910
def : InstRW<[N1Write_2c_1L_1V],
911911
(instregex "ST1Onev(16b|8h|4s|2d)$")>;
912-
def : InstRW<[N1Write_2c_1L_1V, WriteAdr],
912+
def : InstRW<[WriteAdr, N1Write_2c_1L_1V],
913913
(instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
914914

915915
// ASIMD store, 1 element, multiple, 2 reg, D-form
916916
def : InstRW<[N1Write_2c_1L_2V],
917917
(instregex "ST1Twov(8b|4h|2s|1d)$")>;
918-
def : InstRW<[N1Write_2c_1L_2V, WriteAdr],
918+
def : InstRW<[WriteAdr, N1Write_2c_1L_2V],
919919
(instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
920920

921921
// ASIMD store, 1 element, multiple, 2 reg, Q-form
922922
def : InstRW<[N1Write_3c_2L_2V],
923923
(instregex "ST1Twov(16b|8h|4s|2d)$")>;
924-
def : InstRW<[N1Write_3c_2L_2V, WriteAdr],
924+
def : InstRW<[WriteAdr, N1Write_3c_2L_2V],
925925
(instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
926926

927927
// ASIMD store, 1 element, multiple, 3 reg, D-form
928928
def : InstRW<[N1Write_3c_2L_3V],
929929
(instregex "ST1Threev(8b|4h|2s|1d)$")>;
930-
def : InstRW<[N1Write_3c_2L_3V, WriteAdr],
930+
def : InstRW<[WriteAdr, N1Write_3c_2L_3V],
931931
(instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
932932

933933
// ASIMD store, 1 element, multiple, 3 reg, Q-form
934934
def : InstRW<[N1Write_4c_3L_3V],
935935
(instregex "ST1Threev(16b|8h|4s|2d)$")>;
936-
def : InstRW<[N1Write_4c_3L_3V, WriteAdr],
936+
def : InstRW<[WriteAdr, N1Write_4c_3L_3V],
937937
(instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
938938

939939
// ASIMD store, 1 element, multiple, 4 reg, D-form
940940
def : InstRW<[N1Write_3c_2L_2V],
941941
(instregex "ST1Fourv(8b|4h|2s|1d)$")>;
942-
def : InstRW<[N1Write_3c_2L_2V, WriteAdr],
942+
def : InstRW<[WriteAdr, N1Write_3c_2L_2V],
943943
(instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
944944

945945
// ASIMD store, 1 element, multiple, 4 reg, Q-form
946946
def : InstRW<[N1Write_5c_4L_4V],
947947
(instregex "ST1Fourv(16b|8h|4s|2d)$")>;
948-
def : InstRW<[N1Write_5c_4L_4V, WriteAdr],
948+
def : InstRW<[WriteAdr, N1Write_5c_4L_4V],
949949
(instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
950950

951951
// ASIMD store, 1 element, one lane
952952
def : InstRW<[N1Write_4c_1L_1V],
953953
(instregex "ST1i(8|16|32|64)$")>;
954-
def : InstRW<[N1Write_4c_1L_1V, WriteAdr],
954+
def : InstRW<[WriteAdr, N1Write_4c_1L_1V],
955955
(instregex "ST1i(8|16|32|64)_POST$")>;
956956

957957
// ASIMD store, 2 element, multiple, D-form, B/H/S
958958
def : InstRW<[N1Write_4c_1L_1V],
959959
(instregex "ST2Twov(8b|4h|2s)$")>;
960-
def : InstRW<[N1Write_4c_1L_1V, WriteAdr],
960+
def : InstRW<[WriteAdr, N1Write_4c_1L_1V],
961961
(instregex "ST2Twov(8b|4h|2s)_POST$")>;
962962

963963
// ASIMD store, 2 element, multiple, Q-form
964964
def : InstRW<[N1Write_5c_2L_2V],
965965
(instregex "ST2Twov(16b|8h|4s|2d)$")>;
966-
def : InstRW<[N1Write_5c_2L_2V, WriteAdr],
966+
def : InstRW<[WriteAdr, N1Write_5c_2L_2V],
967967
(instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
968968

969969
// ASIMD store, 2 element, one lane
970970
def : InstRW<[N1Write_4c_1L_1V],
971971
(instregex "ST2i(8|16|32|64)$")>;
972-
def : InstRW<[N1Write_4c_1L_1V, WriteAdr],
972+
def : InstRW<[WriteAdr, N1Write_4c_1L_1V],
973973
(instregex "ST2i(8|16|32|64)_POST$")>;
974974

975975
// ASIMD store, 3 element, multiple, D-form, B/H/S
976976
def : InstRW<[N1Write_5c_2L_2V],
977977
(instregex "ST3Threev(8b|4h|2s)$")>;
978-
def : InstRW<[N1Write_5c_2L_2V, WriteAdr],
978+
def : InstRW<[WriteAdr, N1Write_5c_2L_2V],
979979
(instregex "ST3Threev(8b|4h|2s)_POST$")>;
980980

981981
// ASIMD store, 3 element, multiple, Q-form
982982
def : InstRW<[N1Write_6c_3L_3V],
983983
(instregex "ST3Threev(16b|8h|4s|2d)$")>;
984-
def : InstRW<[N1Write_6c_3L_3V, WriteAdr],
984+
def : InstRW<[WriteAdr, N1Write_6c_3L_3V],
985985
(instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
986986

987987
// ASIMD store, 3 element, one lane, B/H/S
988988
def : InstRW<[N1Write_4c_3L_3V],
989989
(instregex "ST3i(8|16|32)$")>;
990-
def : InstRW<[N1Write_4c_3L_3V, WriteAdr],
990+
def : InstRW<[WriteAdr, N1Write_4c_3L_3V],
991991
(instregex "ST3i(8|16|32)_POST$")>;
992992

993993
// ASIMD store, 3 element, one lane, D
994994
def : InstRW<[N1Write_5c_3L_3V],
995995
(instrs ST3i64)>;
996-
def : InstRW<[N1Write_5c_3L_3V, WriteAdr],
996+
def : InstRW<[WriteAdr, N1Write_5c_3L_3V],
997997
(instrs ST3i64_POST)>;
998998

999999
// ASIMD store, 4 element, multiple, D-form, B/H/S
10001000
def : InstRW<[N1Write_7c_3L_3V],
10011001
(instregex "ST4Fourv(8b|4h|2s)$")>;
1002-
def : InstRW<[N1Write_7c_3L_3V, WriteAdr],
1002+
def : InstRW<[WriteAdr, N1Write_7c_3L_3V],
10031003
(instregex "ST4Fourv(8b|4h|2s)_POST$")>;
10041004

10051005
// ASIMD store, 4 element, multiple, Q-form, B/H/S
10061006
def : InstRW<[N1Write_9c_6L_6V],
10071007
(instregex "ST4Fourv(16b|8h|4s)$")>;
1008-
def : InstRW<[N1Write_9c_6L_6V, WriteAdr],
1008+
def : InstRW<[WriteAdr, N1Write_9c_6L_6V],
10091009
(instregex "ST4Fourv(16b|8h|4s)_POST$")>;
10101010

10111011
// ASIMD store, 4 element, multiple, Q-form, D
10121012
def : InstRW<[N1Write_6c_4L_4V],
10131013
(instrs ST4Fourv2d)>;
1014-
def : InstRW<[N1Write_6c_4L_4V, WriteAdr],
1014+
def : InstRW<[WriteAdr, N1Write_6c_4L_4V],
10151015
(instrs ST4Fourv2d_POST)>;
10161016

10171017
// ASIMD store, 4 element, one lane, B/H/S
10181018
def : InstRW<[N1Write_5c_3L_3V],
10191019
(instregex "ST4i(8|16|32)$")>;
1020-
def : InstRW<[N1Write_5c_3L_3V, WriteAdr],
1020+
def : InstRW<[WriteAdr, N1Write_5c_3L_3V],
10211021
(instregex "ST4i(8|16|32)_POST$")>;
10221022

10231023
// ASIMD store, 4 element, one lane, D
10241024
def : InstRW<[N1Write_4c_3L_3V],
10251025
(instrs ST4i64)>;
1026-
def : InstRW<[N1Write_4c_3L_3V, WriteAdr],
1026+
def : InstRW<[WriteAdr, N1Write_4c_3L_3V],
10271027
(instrs ST4i64_POST)>;
10281028

10291029

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