From 206b7e0246a699ef2fc61ab235dec25eae4ed7ae Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 25 Aug 2024 14:23:57 -0700 Subject: [PATCH] [CodeGen] Use MachineInstr::all_defs (NFC) --- llvm/include/llvm/CodeGen/LiveVariables.h | 4 ++-- llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 3 +-- llvm/lib/CodeGen/MachineInstr.cpp | 21 +++++++------------ llvm/lib/CodeGen/ModuloSchedule.cpp | 4 ++-- llvm/lib/CodeGen/RegAllocFast.cpp | 14 ++++--------- llvm/lib/CodeGen/RegisterCoalescer.cpp | 4 ++-- 6 files changed, 19 insertions(+), 31 deletions(-) diff --git a/llvm/include/llvm/CodeGen/LiveVariables.h b/llvm/include/llvm/CodeGen/LiveVariables.h index b73850bb757ec..89d1b5edf3fa6 100644 --- a/llvm/include/llvm/CodeGen/LiveVariables.h +++ b/llvm/include/llvm/CodeGen/LiveVariables.h @@ -253,8 +253,8 @@ class LiveVariables { return false; bool Removed = false; - for (MachineOperand &MO : MI.operands()) { - if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) { + for (MachineOperand &MO : MI.all_defs()) { + if (MO.getReg() == Reg) { MO.setIsDead(false); Removed = true; break; diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp index bccd9b04cd2c5..e40248197c7c7 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -402,8 +402,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction( // Scan the register defs for this instruction and update // live-ranges. - for (const MachineOperand &MO : MI.operands()) { - if (!MO.isReg() || !MO.isDef()) continue; + for (const MachineOperand &MO : MI.all_defs()) { Register Reg = MO.getReg(); if (Reg == 0) continue; // Ignore KILLs and passthru registers for liveness... diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 0f2acdb12389d..f21910ee3a444 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -2125,19 +2125,15 @@ bool MachineInstr::addRegisterDead(Register Reg, } void MachineInstr::clearRegisterDeads(Register Reg) { - for (MachineOperand &MO : operands()) { - if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) - continue; - MO.setIsDead(false); - } + for (MachineOperand &MO : all_defs()) + if (MO.getReg() == Reg) + MO.setIsDead(false); } void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) { - for (MachineOperand &MO : operands()) { - if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0) - continue; - MO.setIsUndef(IsUndef); - } + for (MachineOperand &MO : all_defs()) + if (MO.getReg() == Reg && MO.getSubReg() != 0) + MO.setIsUndef(IsUndef); } void MachineInstr::addRegisterDefined(Register Reg, @@ -2147,9 +2143,8 @@ void MachineInstr::addRegisterDefined(Register Reg, if (MO) return; } else { - for (const MachineOperand &MO : operands()) { - if (MO.isReg() && MO.getReg() == Reg && MO.isDef() && - MO.getSubReg() == 0) + for (const MachineOperand &MO : all_defs()) { + if (MO.getReg() == Reg && MO.getSubReg() == 0) return; } } diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp index 78201d9bfb79a..99c82bc3a2660 100644 --- a/llvm/lib/CodeGen/ModuloSchedule.cpp +++ b/llvm/lib/CodeGen/ModuloSchedule.cpp @@ -2667,8 +2667,8 @@ void ModuloScheduleExpanderMVE::calcNumUnroll() { void ModuloScheduleExpanderMVE::updateInstrDef(MachineInstr *NewMI, ValueMapTy &VRMap, bool LastDef) { - for (MachineOperand &MO : NewMI->operands()) { - if (!MO.isReg() || !MO.getReg().isVirtual() || !MO.isDef()) + for (MachineOperand &MO : NewMI->all_defs()) { + if (!MO.getReg().isVirtual()) continue; Register Reg = MO.getReg(); const TargetRegisterClass *RC = MRI.getRegClass(Reg); diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index 62f7ed29c8c81..6babd5a3f1f96 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -1329,9 +1329,8 @@ void RegAllocFastImpl::findAndSortDefOperandIndexes(const MachineInstr &MI) { // we assign these. SmallVector RegClassDefCounts(TRI->getNumRegClasses(), 0); - for (const MachineOperand &MO : MI.operands()) - if (MO.isReg() && MO.isDef()) - addRegClassDefCounts(RegClassDefCounts, MO.getReg()); + for (const MachineOperand &MO : MI.all_defs()) + addRegClassDefCounts(RegClassDefCounts, MO.getReg()); llvm::sort(DefOperandIndexes, [&](unsigned I0, unsigned I1) { const MachineOperand &MO0 = MI.getOperand(I0); @@ -1481,9 +1480,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) { // Assign virtual register defs. while (ReArrangedImplicitOps) { ReArrangedImplicitOps = false; - for (MachineOperand &MO : MI.operands()) { - if (!MO.isReg() || !MO.isDef()) - continue; + for (MachineOperand &MO : MI.all_defs()) { Register Reg = MO.getReg(); if (Reg.isVirtual()) { ReArrangedImplicitOps = @@ -1499,10 +1496,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) { // Free registers occupied by defs. // Iterate operands in reverse order, so we see the implicit super register // defs first (we added them earlier in case of ). - for (MachineOperand &MO : reverse(MI.operands())) { - if (!MO.isReg() || !MO.isDef()) - continue; - + for (MachineOperand &MO : reverse(MI.all_defs())) { Register Reg = MO.getReg(); // subreg defs don't free the full register. We left the subreg number diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index f6c53f3051c2f..97f8346df0e8f 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -3230,8 +3230,8 @@ void JoinVals::pruneValues(JoinVals &Other, // Also remove dead flags since the joined live range will // continue past this instruction. for (MachineOperand &MO : - Indexes->getInstructionFromIndex(Def)->operands()) { - if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) { + Indexes->getInstructionFromIndex(Def)->all_defs()) { + if (MO.getReg() == Reg) { if (MO.getSubReg() != 0 && MO.isUndef() && !EraseImpDef) MO.setIsUndef(false); MO.setIsDead(false);