From c8fbbe4904679dc81b3c9fb5d5d8ac1ceff37498 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Fri, 20 Sep 2024 16:27:30 +0100 Subject: [PATCH 1/2] [AMDGPU] When allocating VGPRs, VGPR spills are not part of the prologue PRs #69924 and #72140 modified SIInstrInfo::isBasicBlockPrologue to skip over EXEC modifications and spills when allocating VGPRs. But treating VGPR spills as part of the prologue can confuse the register allocator as in #109294, so restrict it to SGPR spills, which were inserted during SGPR allocation which is done in an earlier pass. Fixes: #109294 Fixes: SWDEV-485841 --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 97e8b08270d61..509c5c56e15f5 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -8884,8 +8884,9 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI, // FIXME: Copies inserted in the block prolog for live-range split should also // be included. return IsNullOrVectorRegister && - (isSpill(Opcode) || (!MI.isTerminator() && Opcode != AMDGPU::COPY && - MI.modifiesRegister(AMDGPU::EXEC, &RI))); + (isSGPRSpill(Opcode) || + (!MI.isTerminator() && Opcode != AMDGPU::COPY && + MI.modifiesRegister(AMDGPU::EXEC, &RI))); } MachineInstrBuilder From 7796e26e93899107dc7907cc0ed49e596face70a Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Mon, 30 Sep 2024 12:01:36 +0100 Subject: [PATCH 2/2] Remove irrelevant FIXME --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 509c5c56e15f5..4a5418a6806d8 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -8881,8 +8881,6 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI, } uint16_t Opcode = MI.getOpcode(); - // FIXME: Copies inserted in the block prolog for live-range split should also - // be included. return IsNullOrVectorRegister && (isSGPRSpill(Opcode) || (!MI.isTerminator() && Opcode != AMDGPU::COPY &&