diff --git a/llvm/docs/WritingAnLLVMBackend.rst b/llvm/docs/WritingAnLLVMBackend.rst index f1f07e4681d50..1b9173b1fe139 100644 --- a/llvm/docs/WritingAnLLVMBackend.rst +++ b/llvm/docs/WritingAnLLVMBackend.rst @@ -152,7 +152,7 @@ To make your target actually do something, you need to implement a subclass of ``lib/Target/DummyTargetMachine.cpp``, but any file in the ``lib/Target`` directory will be built and should work. To use LLVM's target independent code generator, you should do what all current machine backends do: create a -subclass of ``LLVMTargetMachine``. (To create a target from scratch, create a +subclass of ``CodeGenTargetMachineImpl``. (To create a target from scratch, create a subclass of ``TargetMachine``.) To get LLVM to actually build and link your target, you need to run ``cmake`` @@ -165,15 +165,15 @@ located in the main ``CMakeLists.txt``. Target Machine ============== -``LLVMTargetMachine`` is designed as a base class for targets implemented with -the LLVM target-independent code generator. The ``LLVMTargetMachine`` class +``CodeGenTargetMachineImpl`` is designed as a base class for targets implemented with +the LLVM target-independent code generator. The ``CodeGenTargetMachineImpl`` class should be specialized by a concrete target class that implements the various -virtual methods. ``LLVMTargetMachine`` is defined as a subclass of -``TargetMachine`` in ``include/llvm/Target/TargetMachine.h``. The -``TargetMachine`` class implementation (``TargetMachine.cpp``) also processes -numerous command-line options. +virtual methods. ``CodeGenTargetMachineImpl`` is defined as a subclass of +``TargetMachine`` in ``include/llvm/CodeGen/CodeGenTargetMachineImpl.h``. The +``TargetMachine`` class implementation (``include/llvm/Target/TargetMachine.cpp``) +also processes numerous command-line options. -To create a concrete target-specific subclass of ``LLVMTargetMachine``, start +To create a concrete target-specific subclass of ``CodeGenTargetMachineImpl``, start by copying an existing ``TargetMachine`` class and header. You should name the files that you create to reflect your specific target. For instance, for the SPARC target, name the files ``SparcTargetMachine.h`` and @@ -197,7 +197,7 @@ simply return a class member. class Module; - class SparcTargetMachine : public LLVMTargetMachine { + class SparcTargetMachine : public CodeGenTargetMachineImpl { const DataLayout DataLayout; // Calculates type size & alignment SparcSubtarget Subtarget; SparcInstrInfo InstrInfo; diff --git a/llvm/include/llvm/CodeGen/CodeGenTargetMachineImpl.h b/llvm/include/llvm/CodeGen/CodeGenTargetMachineImpl.h new file mode 100644 index 0000000000000..7bb4420e555fb --- /dev/null +++ b/llvm/include/llvm/CodeGen/CodeGenTargetMachineImpl.h @@ -0,0 +1,95 @@ +//===-- CodeGenTargetMachineImpl.h ------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file This file describes the CodeGenTargetMachineImpl class, which +/// implements a set of functionality used by \c TargetMachine classes in +/// LLVM that make use of the target-independent code generator. +//===----------------------------------------------------------------------===// +#ifndef LLVM_CODEGEN_CODEGENTARGETMACHINEIMPL_H +#define LLVM_CODEGEN_CODEGENTARGETMACHINEIMPL_H +#include "llvm/Target/TargetMachine.h" + +namespace llvm { + +/// \brief implements a set of functionality in the \c TargetMachine class +/// for targets that make use of the independent code generator (CodeGen) +/// library. Must not be used directly in code unless to inherit its +/// implementation. +class CodeGenTargetMachineImpl : public TargetMachine { +protected: // Can only create subclasses. + CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, + const Triple &TT, StringRef CPU, StringRef FS, + const TargetOptions &Options, Reloc::Model RM, + CodeModel::Model CM, CodeGenOptLevel OL); + + void initAsmInfo(); + + /// Reset internal state. + virtual void reset() {}; + +public: + /// Get a TargetTransformInfo implementation for the target. + /// + /// The TTI returned uses the common code generator to answer queries about + /// the IR. + TargetTransformInfo getTargetTransformInfo(const Function &F) const override; + + /// Create a pass configuration object to be used by addPassToEmitX methods + /// for generating a pipeline of CodeGen passes. + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + + /// Add passes to the specified pass manager to get the specified file + /// emitted. Typically this will involve several steps of code generation. + /// \p MMIWP is an optional parameter that, if set to non-nullptr, + /// will be used to set the MachineModuloInfo for this PM. + bool + addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out, + raw_pwrite_stream *DwoOut, CodeGenFileType FileType, + bool DisableVerify = true, + MachineModuleInfoWrapperPass *MMIWP = nullptr) override; + + /// Add passes to the specified pass manager to get machine code emitted with + /// the MCJIT. This method returns true if machine code is not supported. It + /// fills the MCContext Ctx pointer which can be used to build custom + /// MCStreamer. + bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, + raw_pwrite_stream &Out, + bool DisableVerify = true) override; + + /// Adds an AsmPrinter pass to the pipeline that prints assembly or + /// machine code from the MI representation. + bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out, + raw_pwrite_stream *DwoOut, CodeGenFileType FileType, + MCContext &Context) override; + + Expected> + createMCStreamer(raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, + CodeGenFileType FileType, MCContext &Ctx) override; +}; + +/// Helper method for getting the code model, returning Default if +/// CM does not have a value. The tiny and kernel models will produce +/// an error, so targets that support them or require more complex codemodel +/// selection logic should implement and call their own getEffectiveCodeModel. +inline CodeModel::Model +getEffectiveCodeModel(std::optional CM, + CodeModel::Model Default) { + if (CM) { + // By default, targets do not support the tiny and kernel models. + if (*CM == CodeModel::Tiny) + report_fatal_error("Target does not support the tiny CodeModel", false); + if (*CM == CodeModel::Kernel) + report_fatal_error("Target does not support the kernel CodeModel", false); + return *CM; + } + return Default; +} + +} // namespace llvm + +#endif diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h index 9c5d6555351d0..bb75d5aa8cfa6 100644 --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -54,7 +54,7 @@ class DILocation; class Function; class GISelChangeObserver; class GlobalValue; -class LLVMTargetMachine; +class TargetMachine; class MachineConstantPool; class MachineFrameInfo; class MachineFunction; @@ -256,7 +256,7 @@ struct LandingPadInfo { class LLVM_ABI MachineFunction { Function &F; - const LLVMTargetMachine &Target; + const TargetMachine &Target; const TargetSubtargetInfo *STI; MCContext &Ctx; @@ -633,7 +633,7 @@ class LLVM_ABI MachineFunction { /// for instructions that have a stack spill fused into them. const static unsigned int DebugOperandMemNumber; - MachineFunction(Function &F, const LLVMTargetMachine &Target, + MachineFunction(Function &F, const TargetMachine &Target, const TargetSubtargetInfo &STI, MCContext &Ctx, unsigned FunctionNum); MachineFunction(const MachineFunction &) = delete; @@ -706,7 +706,7 @@ class LLVM_ABI MachineFunction { void assignBeginEndSections(); /// getTarget - Return the target machine this machine code is compiled with - const LLVMTargetMachine &getTarget() const { return Target; } + const TargetMachine &getTarget() const { return Target; } /// getSubtarget - Return the subtarget for which this machine code is being /// compiled. diff --git a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h index f54d455292da0..e194f4838e118 100644 --- a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h +++ b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h @@ -18,7 +18,7 @@ namespace llvm { class MachineFunction; -class LLVMTargetMachine; +class TargetMachine; /// This analysis create MachineFunction for given Function. /// To release the MachineFunction, users should invalidate it explicitly. @@ -28,7 +28,7 @@ class MachineFunctionAnalysis static AnalysisKey Key; - const LLVMTargetMachine *TM; + const TargetMachine *TM; public: class Result { @@ -41,7 +41,7 @@ class MachineFunctionAnalysis FunctionAnalysisManager::Invalidator &); }; - MachineFunctionAnalysis(const LLVMTargetMachine *TM) : TM(TM){}; + MachineFunctionAnalysis(const TargetMachine *TM) : TM(TM) {}; Result run(Function &F, FunctionAnalysisManager &FAM); }; diff --git a/llvm/include/llvm/CodeGen/MachineModuleInfo.h b/llvm/include/llvm/CodeGen/MachineModuleInfo.h index 310cc4b2abb77..bec500dc609f3 100644 --- a/llvm/include/llvm/CodeGen/MachineModuleInfo.h +++ b/llvm/include/llvm/CodeGen/MachineModuleInfo.h @@ -43,7 +43,7 @@ namespace llvm { class Function; -class LLVMTargetMachine; +class TargetMachine; class MachineFunction; class Module; @@ -83,7 +83,7 @@ class MachineModuleInfo { friend class MachineModuleInfoWrapperPass; friend class MachineModuleAnalysis; - const LLVMTargetMachine &TM; + const TargetMachine &TM; /// This is the MCContext used for the entire code generator. MCContext Context; @@ -109,10 +109,9 @@ class MachineModuleInfo { MachineModuleInfo &operator=(MachineModuleInfo &&MMII) = delete; public: - explicit MachineModuleInfo(const LLVMTargetMachine *TM = nullptr); + explicit MachineModuleInfo(const TargetMachine *TM = nullptr); - explicit MachineModuleInfo(const LLVMTargetMachine *TM, - MCContext *ExtContext); + explicit MachineModuleInfo(const TargetMachine *TM, MCContext *ExtContext); MachineModuleInfo(MachineModuleInfo &&MMII); @@ -121,7 +120,7 @@ class MachineModuleInfo { void initialize(); void finalize(); - const LLVMTargetMachine &getTarget() const { return TM; } + const TargetMachine &getTarget() const { return TM; } const MCContext &getContext() const { return ExternalContext ? *ExternalContext : Context; @@ -173,9 +172,9 @@ class MachineModuleInfoWrapperPass : public ImmutablePass { public: static char ID; // Pass identification, replacement for typeid - explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM = nullptr); + explicit MachineModuleInfoWrapperPass(const TargetMachine *TM = nullptr); - explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM, + explicit MachineModuleInfoWrapperPass(const TargetMachine *TM, MCContext *ExtContext); // Initialization and Finalization diff --git a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h index aa1f5ef8110b0..845ed09a852ad 100644 --- a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h +++ b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h @@ -29,7 +29,7 @@ namespace llvm { class Function; -class LLVMTargetMachine; +class TargetMachine; class PhysicalRegisterUsageInfo : public ImmutablePass { public: @@ -41,7 +41,7 @@ class PhysicalRegisterUsageInfo : public ImmutablePass { } /// Set TargetMachine which is used to print analysis. - void setTargetMachine(const LLVMTargetMachine &TM); + void setTargetMachine(const TargetMachine &TM); bool doInitialization(Module &M) override; @@ -63,7 +63,7 @@ class PhysicalRegisterUsageInfo : public ImmutablePass { /// and 1 means content of register will be preserved around function call. DenseMap> RegMasks; - const LLVMTargetMachine *TM = nullptr; + const TargetMachine *TM = nullptr; }; } // end namespace llvm diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h index 53265b286c7c8..54e65335edf3a 100644 --- a/llvm/include/llvm/CodeGen/ScheduleDAG.h +++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h @@ -32,7 +32,7 @@ namespace llvm { template struct GraphTraits; template class GraphWriter; -class LLVMTargetMachine; +class TargetMachine; class MachineFunction; class MachineRegisterInfo; class MCInstrDesc; @@ -571,7 +571,7 @@ class TargetRegisterInfo; class ScheduleDAG { public: - const LLVMTargetMachine &TM; ///< Target processor + const TargetMachine &TM; ///< Target processor const TargetInstrInfo *TII; ///< Target instruction information const TargetRegisterInfo *TRI; ///< Target processor register info MachineFunction &MF; ///< Machine function diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h index 2f5951e3ec3bc..85f87de521855 100644 --- a/llvm/include/llvm/CodeGen/TargetPassConfig.h +++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h @@ -21,7 +21,7 @@ namespace llvm { -class LLVMTargetMachine; +class TargetMachine; struct MachineSchedContext; class PassConfigImpl; class ScheduleDAGInstrs; @@ -120,7 +120,7 @@ class TargetPassConfig : public ImmutablePass { void setStartStopPasses(); protected: - LLVMTargetMachine *TM; + TargetMachine *TM; PassConfigImpl *Impl = nullptr; // Internal data structures bool Initialized = false; // Flagged after all passes are configured. @@ -148,7 +148,7 @@ class TargetPassConfig : public ImmutablePass { bool addCoreISelPasses(); public: - TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm); + TargetPassConfig(TargetMachine &TM, PassManagerBase &PM); // Dummy constructor. TargetPassConfig(); @@ -413,7 +413,7 @@ class TargetPassConfig : public ImmutablePass { virtual void addFastRegAlloc(); /// addOptimizedRegAlloc - Add passes related to register allocation. - /// LLVMTargetMachine provides standard regalloc passes for most targets. + /// CodeGenCommonTMImpl provides standard regalloc passes for most targets. virtual void addOptimizedRegAlloc(); /// addPreRewrite - Add passes to the optimized register allocation pipeline @@ -497,7 +497,7 @@ class TargetPassConfig : public ImmutablePass { }; void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, - LLVMTargetMachine &); + TargetMachine &); } // end namespace llvm diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 3f7d226c7cbff..d04387535db0d 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -443,7 +443,7 @@ template class CodeGenPassBuilder { Error addFastRegAlloc(AddMachinePass &) const; /// addOptimizedRegAlloc - Add passes related to register allocation. - /// LLVMTargetMachine provides standard regalloc passes for most targets. + /// CodeGenCommonTMImpl provides standard regalloc passes for most targets. void addOptimizedRegAlloc(AddMachinePass &) const; /// Add passes that optimize machine instructions after register allocation. diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index fa3ab58a21ddc..9bdb110bd3683 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -5,9 +5,9 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// -// This file defines the TargetMachine and LLVMTargetMachine classes. -// +/// +/// This file defines the TargetMachine class. +/// //===----------------------------------------------------------------------===// #ifndef LLVM_TARGET_TARGETMACHINE_H @@ -16,6 +16,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/PassManager.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Error.h" @@ -40,7 +41,6 @@ class MCAsmInfo; class MCContext; class MCInstrInfo; class MCRegisterInfo; -class MCStreamer; class MCSubtargetInfo; class MCSymbol; class raw_pwrite_stream; @@ -60,13 +60,13 @@ class TargetSubtargetInfo; // The old pass manager infrastructure is hidden in a legacy namespace now. namespace legacy { class PassManagerBase; -} +} // namespace legacy using legacy::PassManagerBase; struct MachineFunctionInfo; namespace yaml { struct MachineFunctionInfo; -} +} // namespace yaml //===----------------------------------------------------------------------===// /// @@ -434,43 +434,12 @@ class TargetMachine { function_ref MPart)> ModuleCallback) { return false; } -}; - -/// This class describes a target machine that is implemented with the LLVM -/// target-independent code generator. -/// -class LLVMTargetMachine : public TargetMachine { -protected: // Can only create subclasses. - LLVMTargetMachine(const Target &T, StringRef DataLayoutString, - const Triple &TT, StringRef CPU, StringRef FS, - const TargetOptions &Options, Reloc::Model RM, - CodeModel::Model CM, CodeGenOptLevel OL); - - void initAsmInfo(); - - /// Reset internal state. - virtual void reset() {}; - -public: - /// Get a TargetTransformInfo implementation for the target. - /// - /// The TTI returned uses the common code generator to answer queries about - /// the IR. - TargetTransformInfo getTargetTransformInfo(const Function &F) const override; /// Create a pass configuration object to be used by addPassToEmitX methods /// for generating a pipeline of CodeGen passes. - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); - - /// Add passes to the specified pass manager to get the specified file - /// emitted. Typically this will involve several steps of code generation. - /// \p MMIWP is an optional parameter that, if set to non-nullptr, - /// will be used to set the MachineModuloInfo for this PM. - bool - addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out, - raw_pwrite_stream *DwoOut, CodeGenFileType FileType, - bool DisableVerify = true, - MachineModuleInfoWrapperPass *MMIWP = nullptr) override; + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM) { + return nullptr; + } virtual Error buildCodeGenPipeline(ModulePassManager &, raw_pwrite_stream &, raw_pwrite_stream *, CodeGenFileType, @@ -480,14 +449,6 @@ class LLVMTargetMachine : public TargetMachine { inconvertibleErrorCode()); } - /// Add passes to the specified pass manager to get machine code emitted with - /// the MCJIT. This method returns true if machine code is not supported. It - /// fills the MCContext Ctx pointer which can be used to build custom - /// MCStreamer. - bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, - raw_pwrite_stream &Out, - bool DisableVerify = true) override; - /// Returns true if the target is expected to pass all machine verifier /// checks. This is a stopgap measure to fix targets one by one. We will /// remove this at some point and always enable the verifier when @@ -496,13 +457,17 @@ class LLVMTargetMachine : public TargetMachine { /// Adds an AsmPrinter pass to the pipeline that prints assembly or /// machine code from the MI representation. - bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out, - raw_pwrite_stream *DwoOut, CodeGenFileType FileType, - MCContext &Context); + virtual bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out, + raw_pwrite_stream *DwoOut, + CodeGenFileType FileType, MCContext &Context) { + return false; + } - Expected> + virtual Expected> createMCStreamer(raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, - CodeGenFileType FileType, MCContext &Ctx); + CodeGenFileType FileType, MCContext &Ctx) { + return nullptr; + } /// True if the target uses physical regs (as nearly all targets do). False /// for stack machines such as WebAssembly and other virtual-register @@ -514,9 +479,7 @@ class LLVMTargetMachine : public TargetMachine { /// True if the target wants to use interprocedural register allocation by /// default. The -enable-ipra flag can be used to override this. - virtual bool useIPRA() const { - return false; - } + virtual bool useIPRA() const { return false; } /// The default variant to use in unqualified `asm` instructions. /// If this returns 0, `asm "$(foo$|bar$)"` will evaluate to `asm "foo"`. @@ -526,24 +489,6 @@ class LLVMTargetMachine : public TargetMachine { virtual void registerMachineRegisterInfoCallback(MachineFunction &MF) const {} }; -/// Helper method for getting the code model, returning Default if -/// CM does not have a value. The tiny and kernel models will produce -/// an error, so targets that support them or require more complex codemodel -/// selection logic should implement and call their own getEffectiveCodeModel. -inline CodeModel::Model -getEffectiveCodeModel(std::optional CM, - CodeModel::Model Default) { - if (CM) { - // By default, targets do not support the tiny and kernel models. - if (*CM == CodeModel::Tiny) - report_fatal_error("Target does not support the tiny CodeModel", false); - if (*CM == CodeModel::Kernel) - report_fatal_error("Target does not support the kernel CodeModel", false); - return *CM; - } - return Default; -} - } // end namespace llvm #endif // LLVM_TARGET_TARGETMACHINE_H diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt index 5f0496a013795..7b47c0e6f75db 100644 --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -100,7 +100,7 @@ add_llvm_component_library(LLVMCodeGen LiveRegUnits.cpp LiveStacks.cpp LiveVariables.cpp - LLVMTargetMachine.cpp + CodeGenTargetMachineImpl.cpp LocalStackSlotAllocation.cpp LoopTraversal.cpp LowLevelTypeUtils.cpp diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp similarity index 84% rename from llvm/lib/CodeGen/LLVMTargetMachine.cpp rename to llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp index ea36fedef93ac..5757ca1b3adf8 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp @@ -1,16 +1,16 @@ -//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===// +//===-- CodeGenTargetMachineImpl.cpp --------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// -// This file implements the LLVMTargetMachine class. -// +/// +/// \file This file implements the CodeGenTargetMachineImpl class. +/// //===----------------------------------------------------------------------===// -#include "llvm/Analysis/Passes.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/CodeGen/MachineModuleInfo.h" @@ -42,7 +42,7 @@ static cl::opt EnableNoTrapAfterNoreturn( cl::desc("Do not emit a trap instruction for 'unreachable' IR instructions " "after noreturn calls, even if --trap-unreachable is set.")); -void LLVMTargetMachine::initAsmInfo() { +void CodeGenTargetMachineImpl::initAsmInfo() { MRI.reset(TheTarget.createMCRegInfo(getTargetTriple().str())); assert(MRI && "Unable to create reg info"); MII.reset(TheTarget.createMCInstrInfo()); @@ -62,8 +62,8 @@ void LLVMTargetMachine::initAsmInfo() { // we'll crash later. // Provide the user with a useful error message about what's wrong. assert(TmpAsmInfo && "MCAsmInfo not initialized. " - "Make sure you include the correct TargetSelect.h" - "and that InitializeAllTargetMCs() is being invoked!"); + "Make sure you include the correct TargetSelect.h" + "and that InitializeAllTargetMCs() is being invoked!"); if (Options.BinutilsVersion.first > 0) TmpAsmInfo->setBinutilsVersion(Options.BinutilsVersion); @@ -85,12 +85,10 @@ void LLVMTargetMachine::initAsmInfo() { AsmInfo.reset(TmpAsmInfo); } -LLVMTargetMachine::LLVMTargetMachine(const Target &T, - StringRef DataLayoutString, - const Triple &TT, StringRef CPU, - StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, - CodeGenOptLevel OL) +CodeGenTargetMachineImpl::CodeGenTargetMachineImpl( + const Target &T, StringRef DataLayoutString, const Triple &TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, + CodeModel::Model CM, CodeGenOptLevel OL) : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) { this->RM = RM; this->CMModel = CM; @@ -103,13 +101,13 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, } TargetTransformInfo -LLVMTargetMachine::getTargetTransformInfo(const Function &F) const { +CodeGenTargetMachineImpl::getTargetTransformInfo(const Function &F) const { return TargetTransformInfo(BasicTTIImpl(this, F)); } /// addPassesToX helper drives creation and initialization of TargetPassConfig. static TargetPassConfig * -addPassesToGenerateCode(LLVMTargetMachine &TM, PassManagerBase &PM, +addPassesToGenerateCode(CodeGenTargetMachineImpl &TM, PassManagerBase &PM, bool DisableVerify, MachineModuleInfoWrapperPass &MMIWP) { // Targets may override createPassConfig to provide a target-specific @@ -127,11 +125,11 @@ addPassesToGenerateCode(LLVMTargetMachine &TM, PassManagerBase &PM, return PassConfig; } -bool LLVMTargetMachine::addAsmPrinter(PassManagerBase &PM, - raw_pwrite_stream &Out, - raw_pwrite_stream *DwoOut, - CodeGenFileType FileType, - MCContext &Context) { +bool CodeGenTargetMachineImpl::addAsmPrinter(PassManagerBase &PM, + raw_pwrite_stream &Out, + raw_pwrite_stream *DwoOut, + CodeGenFileType FileType, + MCContext &Context) { Expected> MCStreamerOrErr = createMCStreamer(Out, DwoOut, FileType, Context); if (auto Err = MCStreamerOrErr.takeError()) @@ -147,9 +145,11 @@ bool LLVMTargetMachine::addAsmPrinter(PassManagerBase &PM, return false; } -Expected> LLVMTargetMachine::createMCStreamer( - raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType, - MCContext &Context) { +Expected> +CodeGenTargetMachineImpl::createMCStreamer(raw_pwrite_stream &Out, + raw_pwrite_stream *DwoOut, + CodeGenFileType FileType, + MCContext &Context) { const MCSubtargetInfo &STI = *getMCSubtargetInfo(); const MCAsmInfo &MAI = *getMCAsmInfo(); const MCRegisterInfo &MRI = *getMCRegisterInfo(); @@ -208,7 +208,7 @@ Expected> LLVMTargetMachine::createMCStreamer( return std::move(AsmStreamer); } -bool LLVMTargetMachine::addPassesToEmitFile( +bool CodeGenTargetMachineImpl::addPassesToEmitFile( PassManagerBase &PM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType, bool DisableVerify, MachineModuleInfoWrapperPass *MMIWP) { @@ -238,9 +238,10 @@ bool LLVMTargetMachine::addPassesToEmitFile( /// code is not supported. It fills the MCContext Ctx pointer which can be /// used to build custom MCStreamer. /// -bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, - raw_pwrite_stream &Out, - bool DisableVerify) { +bool CodeGenTargetMachineImpl::addPassesToEmitMC(PassManagerBase &PM, + MCContext *&Ctx, + raw_pwrite_stream &Out, + bool DisableVerify) { // Add common CodeGen passes. MachineModuleInfoWrapperPass *MMIWP = new MachineModuleInfoWrapperPass(this); TargetPassConfig *PassConfig = diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index c0c61b3fdd167..e2543f883f91c 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -314,7 +314,7 @@ bool MIRParserImpl::parseMachineFunction(Module &M, MachineModuleInfo &MMI, yaml::MachineFunction YamlMF; yaml::EmptyContext Ctx; - const LLVMTargetMachine &TM = MMI.getTarget(); + const TargetMachine &TM = MMI.getTarget(); YamlMF.MachineFuncInfo = std::unique_ptr( TM.createDefaultFuncInfoYAML()); @@ -461,7 +461,7 @@ bool MIRParserImpl::initializeCallSiteInfo( PerFunctionMIParsingState &PFS, const yaml::MachineFunction &YamlMF) { MachineFunction &MF = PFS.MF; SMDiagnostic Error; - const LLVMTargetMachine &TM = MF.getTarget(); + const TargetMachine &TM = MF.getTarget(); for (auto &YamlCSInfo : YamlMF.CallSitesInfo) { yaml::CallSiteInfo::MachineInstrLoc MILoc = YamlCSInfo.CallLocation; if (MILoc.BlockNum >= MF.size()) @@ -615,7 +615,7 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF, return true; if (YamlMF.MachineFuncInfo) { - const LLVMTargetMachine &TM = MF.getTarget(); + const TargetMachine &TM = MF.getTarget(); // Note this is called after the initial constructor of the // MachineFunctionInfo based on the MachineFunction, which may depend on the // IR. diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index 18c2247f86474..a293a77d3fae9 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -160,7 +160,7 @@ static inline Align getFnStackAlignment(const TargetSubtargetInfo *STI, return STI->getFrameLowering()->getStackAlign(); } -MachineFunction::MachineFunction(Function &F, const LLVMTargetMachine &Target, +MachineFunction::MachineFunction(Function &F, const TargetMachine &Target, const TargetSubtargetInfo &STI, MCContext &Ctx, unsigned FunctionNum) : F(F), Target(Target), STI(&STI), Ctx(Ctx) { diff --git a/llvm/lib/CodeGen/MachineModuleInfo.cpp b/llvm/lib/CodeGen/MachineModuleInfo.cpp index c66495969b4e6..6167e99aecf03 100644 --- a/llvm/lib/CodeGen/MachineModuleInfo.cpp +++ b/llvm/lib/CodeGen/MachineModuleInfo.cpp @@ -48,7 +48,7 @@ MachineModuleInfo::MachineModuleInfo(MachineModuleInfo &&MMI) TheModule = MMI.TheModule; } -MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM) +MachineModuleInfo::MachineModuleInfo(const TargetMachine *TM) : TM(*TM), Context(TM->getTargetTriple(), TM->getMCAsmInfo(), TM->getMCRegisterInfo(), TM->getMCSubtargetInfo(), nullptr, &TM->Options.MCOptions, false) { @@ -56,7 +56,7 @@ MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM) initialize(); } -MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM, +MachineModuleInfo::MachineModuleInfo(const TargetMachine *TM, MCContext *ExtContext) : TM(*TM), Context(TM->getTargetTriple(), TM->getMCAsmInfo(), TM->getMCRegisterInfo(), TM->getMCSubtargetInfo(), @@ -151,13 +151,13 @@ FunctionPass *llvm::createFreeMachineFunctionPass() { } MachineModuleInfoWrapperPass::MachineModuleInfoWrapperPass( - const LLVMTargetMachine *TM) + const TargetMachine *TM) : ImmutablePass(ID), MMI(TM) { initializeMachineModuleInfoWrapperPassPass(*PassRegistry::getPassRegistry()); } MachineModuleInfoWrapperPass::MachineModuleInfoWrapperPass( - const LLVMTargetMachine *TM, MCContext *ExtContext) + const TargetMachine *TM, MCContext *ExtContext) : ImmutablePass(ID), MMI(TM, ExtContext) { initializeMachineModuleInfoWrapperPassPass(*PassRegistry::getPassRegistry()); } diff --git a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp index ca5e0b428c477..44524cc9f96cc 100644 --- a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp +++ b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp @@ -100,7 +100,7 @@ static bool isCallableFunction(const MachineFunction &MF) { bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { MachineRegisterInfo *MRI = &MF.getRegInfo(); const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); - const LLVMTargetMachine &TM = MF.getTarget(); + const TargetMachine &TM = MF.getTarget(); LLVM_DEBUG(dbgs() << " -------------------- " << getPassName() << " -------------------- \nFunction Name : " diff --git a/llvm/lib/CodeGen/RegisterUsageInfo.cpp b/llvm/lib/CodeGen/RegisterUsageInfo.cpp index 51bac3fc0a233..1b1be98c23294 100644 --- a/llvm/lib/CodeGen/RegisterUsageInfo.cpp +++ b/llvm/lib/CodeGen/RegisterUsageInfo.cpp @@ -37,7 +37,7 @@ INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info", char PhysicalRegisterUsageInfo::ID = 0; -void PhysicalRegisterUsageInfo::setTargetMachine(const LLVMTargetMachine &TM) { +void PhysicalRegisterUsageInfo::setTargetMachine(const TargetMachine &TM) { this->TM = &TM; } diff --git a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp index 11bdf3bb2ba8c..0cebad42c0ff8 100644 --- a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp +++ b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp @@ -69,7 +69,7 @@ namespace { MF.reset(); MF.initTargetMachineFunctionInfo(MF.getSubtarget()); - const LLVMTargetMachine &TM = MF.getTarget(); + const TargetMachine &TM = MF.getTarget(); // MRI callback for target specific initializations. TM.registerMachineRegisterInfoCallback(MF); diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 5f3fe12cad7df..249407ff1c921 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -22,6 +22,7 @@ #include "llvm/Analysis/TypeBasedAliasAnalysis.h" #include "llvm/CodeGen/BasicBlockSectionsProfileReader.h" #include "llvm/CodeGen/CSEConfigBase.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachinePassRegistry.h" #include "llvm/CodeGen/Passes.h" @@ -514,7 +515,7 @@ CGPassBuilderOption llvm::getCGPassBuilderOption() { } void llvm::registerCodeGenCallback(PassInstrumentationCallbacks &PIC, - LLVMTargetMachine &LLVMTM) { + TargetMachine &TM) { // Register a callback for disabling passes. PIC.registerShouldRunOptionalPassCallback([](StringRef P, Any) { @@ -577,8 +578,8 @@ TargetPassConfig::getStartStopInfo(PassInstrumentationCallbacks &PIC) { // Out of line constructor provides default values for pass options and // registers all common codegen passes. -TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm) - : ImmutablePass(ID), PM(&pm), TM(&TM) { +TargetPassConfig::TargetPassConfig(TargetMachine &TM, PassManagerBase &PM) + : ImmutablePass(ID), PM(&PM), TM(&TM) { Impl = new PassConfigImpl(); // Register all target independent codegen passes to activate their PassIDs, @@ -624,7 +625,8 @@ void TargetPassConfig::insertPass(AnalysisID TargetPassID, /// addPassToEmitX methods for generating a pipeline of CodeGen passes. /// /// Targets may override this to extend TargetPassConfig. -TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { +TargetPassConfig * +CodeGenTargetMachineImpl::createPassConfig(PassManagerBase &PM) { return new TargetPassConfig(*this, PM); } diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 21d53e5d01fbc..9130bc05e87db 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -284,9 +284,7 @@ FUNCTION_ANALYSIS("demanded-bits", DemandedBitsAnalysis()) FUNCTION_ANALYSIS("domfrontier", DominanceFrontierAnalysis()) FUNCTION_ANALYSIS("domtree", DominatorTreeAnalysis()) FUNCTION_ANALYSIS("func-properties", FunctionPropertiesAnalysis()) -FUNCTION_ANALYSIS( - "machine-function-info", - MachineFunctionAnalysis(static_cast(TM))) +FUNCTION_ANALYSIS("machine-function-info", MachineFunctionAnalysis(TM)) FUNCTION_ANALYSIS("gc-function", GCFunctionAnalysis()) FUNCTION_ANALYSIS("inliner-size-estimator", InlineSizeEstimatorAnalysis()) FUNCTION_ANALYSIS("last-run-tracking", LastRunTrackingAnalysis()) diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index c588f2ccf42f0..074f39c19fdb2 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -357,11 +357,11 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT, std::optional CM, CodeGenOptLevel OL, bool JIT, bool LittleEndian) - : LLVMTargetMachine(T, - computeDataLayout(TT, Options.MCOptions, LittleEndian), - TT, computeDefaultCPU(TT, CPU), FS, Options, - getEffectiveRelocModel(TT, RM), - getEffectiveAArch64CodeModel(TT, CM, JIT), OL), + : CodeGenTargetMachineImpl( + T, computeDataLayout(TT, Options.MCOptions, LittleEndian), TT, + computeDefaultCPU(TT, CPU), FS, Options, + getEffectiveRelocModel(TT, RM), + getEffectiveAArch64CodeModel(TT, CM, JIT), OL), TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) { initAsmInfo(); diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h index e4d0aff50d8f6..76b1c9d917ecd 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h @@ -15,13 +15,13 @@ #include "AArch64InstrInfo.h" #include "AArch64Subtarget.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/IR/DataLayout.h" -#include "llvm/Target/TargetMachine.h" #include namespace llvm { -class AArch64TargetMachine : public LLVMTargetMachine { +class AArch64TargetMachine : public CodeGenTargetMachineImpl { protected: std::unique_ptr TLOF; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp index be7b92c5b2524..413f2b1cdb753 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp @@ -95,7 +95,7 @@ void MCResourceInfo::assignResourceInfoExpr( int64_t LocalValue, ResourceInfoKind RIK, AMDGPUMCExpr::VariantKind Kind, const MachineFunction &MF, const SmallVectorImpl &Callees, MCContext &OutContext) { - const LLVMTargetMachine &TM = MF.getTarget(); + const TargetMachine &TM = MF.getTarget(); MCSymbol *FnSym = TM.getSymbol(&MF.getFunction()); const MCConstantExpr *LocalConstExpr = MCConstantExpr::create(LocalValue, OutContext); @@ -137,7 +137,7 @@ void MCResourceInfo::gatherResourceInfo( addMaxSGPRCandidate(FRI.NumExplicitSGPR); } - const LLVMTargetMachine &TM = MF.getTarget(); + const TargetMachine &TM = MF.getTarget(); MCSymbol *FnSym = TM.getSymbol(&MF.getFunction()); auto SetMaxReg = [&](MCSymbol *MaxSym, int32_t numRegs, @@ -221,7 +221,7 @@ void MCResourceInfo::gatherResourceInfo( const MCExpr *MCResourceInfo::createTotalNumVGPRs(const MachineFunction &MF, MCContext &Ctx) { - const LLVMTargetMachine &TM = MF.getTarget(); + const TargetMachine &TM = MF.getTarget(); MCSymbol *FnSym = TM.getSymbol(&MF.getFunction()); return AMDGPUMCExpr::createTotalNumVGPR( getSymRefExpr(FnSym->getName(), RIK_NumAGPR, Ctx), @@ -231,7 +231,7 @@ const MCExpr *MCResourceInfo::createTotalNumVGPRs(const MachineFunction &MF, const MCExpr *MCResourceInfo::createTotalNumSGPRs(const MachineFunction &MF, bool hasXnack, MCContext &Ctx) { - const LLVMTargetMachine &TM = MF.getTarget(); + const TargetMachine &TM = MF.getTarget(); MCSymbol *FnSym = TM.getSymbol(&MF.getFunction()); return MCBinaryExpr::createAdd( getSymRefExpr(FnSym->getName(), RIK_NumSGPR, Ctx), diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 7cfff7c2f8ac0..603339e200dde 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -659,9 +659,10 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OptLevel) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), - FS, Options, getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM, CodeModel::Small), OptLevel), + : CodeGenTargetMachineImpl( + T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), FS, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, CodeModel::Small), OptLevel), TLOF(createTLOF(getTargetTriple())) { initAsmInfo(); if (TT.getArch() == Triple::amdgcn) { @@ -1007,8 +1008,8 @@ namespace { class GCNPassConfig final : public AMDGPUPassConfig { public: - GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM) - : AMDGPUPassConfig(TM, PM) { + GCNPassConfig(TargetMachine &TM, PassManagerBase &PM) + : AMDGPUPassConfig(TM, PM) { // It is necessary to know the register usage of the entire call graph. We // allow calls without EnableAMDGPUFunctionCalls if they are marked // noinline, so this is always required. @@ -1070,7 +1071,7 @@ class GCNPassConfig final : public AMDGPUPassConfig { } // end anonymous namespace -AMDGPUPassConfig::AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM) +AMDGPUPassConfig::AMDGPUPassConfig(TargetMachine &TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) { // Exceptions and StackMaps are not supported, so these passes will never do // anything. diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index d8a5111e5898d..5ba58a92621ed 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -15,10 +15,10 @@ #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H #include "GCNSubtarget.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/MC/MCStreamer.h" #include "llvm/Passes/CodeGenPassBuilder.h" -#include "llvm/Target/TargetMachine.h" #include #include @@ -28,7 +28,7 @@ namespace llvm { // AMDGPU Target Machine (R600+) //===----------------------------------------------------------------------===// -class AMDGPUTargetMachine : public LLVMTargetMachine { +class AMDGPUTargetMachine : public CodeGenTargetMachineImpl { protected: std::unique_ptr TLOF; @@ -123,7 +123,7 @@ class GCNTargetMachine final : public AMDGPUTargetMachine { class AMDGPUPassConfig : public TargetPassConfig { public: - AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM); + AMDGPUPassConfig(TargetMachine &TM, PassManagerBase &PM); AMDGPUTargetMachine &getAMDGPUTargetMachine() const { return getTM(); diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp index a1a60b8bdfa9e..a9e5327d2c6c8 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp @@ -93,7 +93,7 @@ R600TargetMachine::getTargetTransformInfo(const Function &F) const { namespace { class R600PassConfig final : public AMDGPUPassConfig { public: - R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM) + R600PassConfig(TargetMachine &TM, PassManagerBase &PM) : AMDGPUPassConfig(TM, PM) {} ScheduleDAGInstrs * diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp index 5f021cf1f442e..df8c96a4d9793 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -33,11 +33,11 @@ ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, - "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" - "f32:32:32-i64:32-f64:32-a:0:32-n32", - TT, CPU, FS, Options, getRelocModel(RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenCommonTMImpl(T, + "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" + "f32:32:32-i64:32-f64:32-a:0:32-n32", + TT, CPU, FS, Options, getRelocModel(RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()), Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.h b/llvm/lib/Target/ARC/ARCTargetMachine.h index 0fc4243ab44a7..4a46acce51ff2 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.h +++ b/llvm/lib/Target/ARC/ARCTargetMachine.h @@ -14,14 +14,14 @@ #define LLVM_LIB_TARGET_ARC_ARCTARGETMACHINE_H #include "ARCSubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { class TargetPassConfig; -class ARCTargetMachine : public LLVMTargetMachine { +class ARCTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; ARCSubtarget Subtarget; diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 360cd7272ca70..8e7b756b67905 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -220,9 +220,10 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool isLittle) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, - CPU, FS, Options, getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT, CPU, Options, isLittle), + TT, CPU, FS, Options, + getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TargetABI(computeTargetABI(TT, CPU, Options)), TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) { diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h index 5b3594a4dcca8..94d48fcae15eb 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.h +++ b/llvm/lib/Target/ARM/ARMTargetMachine.h @@ -17,6 +17,7 @@ #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" #include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/Support/CodeGen.h" #include "llvm/Target/TargetMachine.h" #include @@ -24,7 +25,7 @@ namespace llvm { -class ARMBaseTargetMachine : public LLVMTargetMachine { +class ARMBaseTargetMachine : public CodeGenTargetMachineImpl { public: enum ARMABI { ARM_ABI_UNKNOWN, diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp index a8c967f865c0c..6851f575cc82f 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -49,9 +49,9 @@ AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options, - getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, AVRDataLayout, TT, getCPU(CPU), FS, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), SubTarget(TT, std::string(getCPU(CPU)), std::string(FS), *this) { this->TLOF = std::make_unique(); initAsmInfo(); diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.h b/llvm/lib/Target/AVR/AVRTargetMachine.h index c19df2bc301ea..167d0076e9581 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.h +++ b/llvm/lib/Target/AVR/AVRTargetMachine.h @@ -13,8 +13,8 @@ #ifndef LLVM_AVR_TARGET_MACHINE_H #define LLVM_AVR_TARGET_MACHINE_H +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/IR/DataLayout.h" -#include "llvm/Target/TargetMachine.h" #include "AVRFrameLowering.h" #include "AVRISelLowering.h" @@ -27,7 +27,7 @@ namespace llvm { /// A generic AVR implementation. -class AVRTargetMachine : public LLVMTargetMachine { +class AVRTargetMachine : public CodeGenTargetMachineImpl { public: AVRTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 578b2d607036b..fac86ad2bace1 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -69,9 +69,9 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()), Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.h b/llvm/lib/Target/BPF/BPFTargetMachine.h index 4e6adc722e76a..15230bd06dadb 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.h +++ b/llvm/lib/Target/BPF/BPFTargetMachine.h @@ -14,11 +14,11 @@ #define LLVM_LIB_TARGET_BPF_BPFTARGETMACHINE_H #include "BPFSubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { -class BPFTargetMachine : public LLVMTargetMachine { +class BPFTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; BPFSubtarget Subtarget; diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp index a756061e307a4..c256bb2d6a4cd 100644 --- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp +++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp @@ -54,9 +54,9 @@ CSKYTargetMachine::CSKYTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - RM.value_or(Reloc::Static), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenCommonTMImpl(T, computeDataLayout(TT), TT, CPU, FS, Options, + RM.value_or(Reloc::Static), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()) { initAsmInfo(); } diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.h b/llvm/lib/Target/CSKY/CSKYTargetMachine.h index e47b514ae9ddc..da0ff31f36dcd 100644 --- a/llvm/lib/Target/CSKY/CSKYTargetMachine.h +++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.h @@ -14,13 +14,13 @@ #define LLVM_LIB_TARGET_CSKY_CSKYTARGETMACHINE_H #include "CSKYSubtarget.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/IR/DataLayout.h" -#include "llvm/Target/TargetMachine.h" #include namespace llvm { -class CSKYTargetMachine : public LLVMTargetMachine { +class CSKYTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp index 59dbf053d6c22..914aee4f8b4b9 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp +++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp @@ -108,11 +108,11 @@ DirectXTargetMachine::DirectXTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, - "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-" - "f32:32-f64:64-n8:16:32:64", - TT, CPU, FS, Options, Reloc::Static, CodeModel::Small, - OL), + : CodeGenCommonTMImpl( + T, + "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-" + "f32:32-f64:64-n8:16:32:64", + TT, CPU, FS, Options, Reloc::Static, CodeModel::Small, OL), TLOF(std::make_unique()), Subtarget(std::make_unique(TT, CPU, FS, *this)) { initAsmInfo(); diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.h b/llvm/lib/Target/DirectX/DirectXTargetMachine.h index d04c375b2736d..7ba80d2ba5de1 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetMachine.h +++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.h @@ -12,12 +12,12 @@ #define LLVM_DIRECTX_DIRECTXTARGETMACHINE_H #include "DirectXSubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { class Function; -class DirectXTargetMachine : public LLVMTargetMachine { +class DirectXTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; std::unique_ptr Subtarget; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 803b9b81045c6..bc8b1d5f76b31 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -274,7 +274,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, // Specify the vector alignment explicitly. For v512x1, the calculated // alignment would be 512*alignment(i1), which is 512 bytes, instead of // the required minimum of 64 bytes. - : LLVMTargetMachine( + : CodeGenTargetMachineImpl( T, "e-m:e-p:32:32:32-a:0-n16:32-" "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h index 6e9a78b766504..6438d0d5a6ba8 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -16,12 +16,12 @@ #include "HexagonInstrInfo.h" #include "HexagonSubtarget.h" #include "HexagonTargetObjectFile.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { -class HexagonTargetMachine : public LLVMTargetMachine { +class HexagonTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; HexagonSubtarget Subtarget; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp index 68eb12f87d89a..fb6df98e61f41 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -60,10 +60,10 @@ LanaiTargetMachine::LanaiTargetMachine( const TargetOptions &Options, std::optional RM, std::optional CodeModel, CodeGenOptLevel OptLevel, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, - getEffectiveRelocModel(RM), - getEffectiveCodeModel(CodeModel, CodeModel::Medium), - OptLevel), + : CodeGenTargetMachineImpl( + T, computeDataLayout(), TT, Cpu, FeatureString, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CodeModel, CodeModel::Medium), OptLevel), Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(), OptLevel), TLOF(new LanaiTargetObjectFile()) { diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.h b/llvm/lib/Target/Lanai/LanaiTargetMachine.h index c5c351b36b316..dc59c33a33f22 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.h +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.h @@ -17,12 +17,12 @@ #include "LanaiInstrInfo.h" #include "LanaiSelectionDAGInfo.h" #include "LanaiSubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { -class LanaiTargetMachine : public LLVMTargetMachine { +class LanaiTargetMachine : public CodeGenTargetMachineImpl { LanaiSubtarget Subtarget; std::unique_ptr TLOF; diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp index 4401aadfe7848..b611365f608af 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp @@ -89,9 +89,9 @@ LoongArchTargetMachine::LoongArchTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(TT, RM), - getEffectiveLoongArchCodeModel(TT, CM), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(TT, RM), + getEffectiveLoongArchCodeModel(TT, CM), OL), TLOF(std::make_unique()) { initAsmInfo(); } diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h index fa9bc7608e7d2..acd3a4a9555b3 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h +++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h @@ -14,12 +14,12 @@ #define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHTARGETMACHINE_H #include "LoongArchSubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { -class LoongArchTargetMachine : public LLVMTargetMachine { +class LoongArchTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp index 2248837e6ca61..ce5970c5ec95d 100644 --- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp +++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp @@ -100,9 +100,9 @@ M68kTargetMachine::M68kTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, - Options, getEffectiveRelocModel(TT, RM), - ::getEffectiveCodeModel(CM, JIT), OL), + : CodeGenCommonTMImpl(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, + Options, getEffectiveRelocModel(TT, RM), + ::getEffectiveCodeModel(CM, JIT), OL), TLOF(std::make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.h b/llvm/lib/Target/M68k/M68kTargetMachine.h index 4ff4c4cb46b80..c2648f5d38c5e 100644 --- a/llvm/lib/Target/M68k/M68kTargetMachine.h +++ b/llvm/lib/Target/M68k/M68kTargetMachine.h @@ -17,10 +17,10 @@ #include "M68kSubtarget.h" #include "MCTargetDesc/M68kMCTargetDesc.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/TargetFrameLowering.h" -#include "llvm/Target/TargetMachine.h" #include @@ -28,7 +28,7 @@ namespace llvm { class formatted_raw_ostream; class M68kRegisterInfo; -class M68kTargetMachine : public LLVMTargetMachine { +class M68kTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; M68kSubtarget Subtarget; diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index f307c37651507..fcfce1d2557dc 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -44,9 +44,9 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, - Options, getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT, CPU, Options), TT, CPU, + FS, Options, getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()), Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.h b/llvm/lib/Target/MSP430/MSP430TargetMachine.h index f9af9a7e26f69..393461cec4bf6 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.h +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.h @@ -15,7 +15,7 @@ #define LLVM_LIB_TARGET_MSP430_MSP430TARGETMACHINE_H #include "MSP430Subtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { @@ -23,7 +23,7 @@ class StringRef; /// MSP430TargetMachine /// -class MSP430TargetMachine : public LLVMTargetMachine { +class MSP430TargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; MSP430Subtarget Subtarget; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index cca4a9cc80566..a388b44b3ac83 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -805,8 +805,8 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S, ELFObjectWriter &W = getStreamer().getWriter(); // It's possible that MCObjectFileInfo isn't fully initialized at this point - // due to an initialization order problem where LLVMTargetMachine creates the - // target streamer before TargetLoweringObjectFile calls + // due to an initialization order problem where CodeGenCommonTMImpl creates + // the target streamer before TargetLoweringObjectFile calls // InitializeMCObjectFileInfo. There doesn't seem to be a single place that // covers all cases so this statement covers most cases and direct object // emission must call setPic() once MCObjectFileInfo has been initialized. The diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 2fb1b922acde4..7fbff116bec5b 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -129,9 +129,10 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, std::optional CM, CodeGenOptLevel OL, bool JIT, bool isLittle) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, - CPU, FS, Options, getEffectiveRelocModel(JIT, RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT, CPU, Options, isLittle), + TT, CPU, FS, Options, + getEffectiveRelocModel(JIT, RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), isLittle(isLittle), TLOF(createTLOF(getTargetTriple())), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), Subtarget(nullptr), diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h index 0ad239e3bed12..321d149f3f7fb 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.h +++ b/llvm/lib/Target/Mips/MipsTargetMachine.h @@ -17,14 +17,14 @@ #include "MipsSubtarget.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/Support/CodeGen.h" -#include "llvm/Target/TargetMachine.h" #include #include namespace llvm { -class MipsTargetMachine : public LLVMTargetMachine { +class MipsTargetMachine : public CodeGenTargetMachineImpl { bool isLittle; std::unique_ptr TLOF; // Selected ABI diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp index 7f4e1035e7a70..f60091f38f246 100644 --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp @@ -209,8 +209,8 @@ bool NVPTXAsmPrinter::lowerImageHandleOperand(const MachineInstr *MI, void NVPTXAsmPrinter::lowerImageHandleSymbol(unsigned Index, MCOperand &MCOp) { // Ewwww - LLVMTargetMachine &TM = const_cast(MF->getTarget()); - NVPTXTargetMachine &nvTM = static_cast(TM); + TargetMachine &TM = const_cast(MF->getTarget()); + NVPTXTargetMachine &nvTM = static_cast(TM); const NVPTXMachineFunctionInfo *MFI = MF->getInfo(); const char *Sym = MFI->getImageHandleSymbol(Index); StringRef SymName = nvTM.getStrPool().save(Sym); diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 31eb0b4fd7b72..9611f5f4f00f0 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -153,9 +153,10 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT, CodeGenOptLevel OL, bool is64bit) // The pic relocation model is used regardless of what the client has // specified, as it is the only relocation model currently supported. - : LLVMTargetMachine(T, computeDataLayout(is64bit, UseShortPointersOpt), TT, - CPU, FS, Options, Reloc::PIC_, - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, + computeDataLayout(is64bit, UseShortPointersOpt), + TT, CPU, FS, Options, Reloc::PIC_, + getEffectiveCodeModel(CM, CodeModel::Small), OL), is64bit(is64bit), TLOF(std::make_unique()), Subtarget(TT, std::string(CPU), std::string(FS), *this), StrPool(StrAlloc) { diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h index 2b88da67a50f9..34d841cd28404 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -14,7 +14,7 @@ #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H #include "NVPTXSubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include #include @@ -22,7 +22,7 @@ namespace llvm { /// NVPTXTargetMachine /// -class NVPTXTargetMachine : public LLVMTargetMachine { +class NVPTXTargetMachine : public CodeGenTargetMachineImpl { bool is64bit; std::unique_ptr TLOF; NVPTX::DrvInterface drvInterface; diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 9cfe030c9e06a..1f6866383e606 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -345,18 +345,18 @@ static ScheduleDAGInstrs *createPPCPostMachineScheduler( // The FeatureString here is a little subtle. We are modifying the feature // string with what are (currently) non-function specific overrides as it goes -// into the LLVMTargetMachine constructor and then using the stored value in the -// Subtarget constructor below it. +// into the CodeGenCommonTMImpl constructor and then using the stored value in +// the Subtarget constructor below it. PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU, - computeFSAdditions(FS, OL, TT), Options, - getEffectiveRelocModel(TT, RM), - getEffectivePPCCodeModel(TT, CM, JIT), OL), + : CodeGenTargetMachineImpl(T, getDataLayoutString(TT), TT, CPU, + computeFSAdditions(FS, OL, TT), Options, + getEffectiveRelocModel(TT, RM), + getEffectivePPCCodeModel(TT, CM, JIT), OL), TLOF(createTLOF(getTargetTriple())), TargetABI(computeTargetABI(TT, Options)), Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) { diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h index 9d0d3e727170a..026bf2f26a816 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h @@ -15,15 +15,15 @@ #include "PPCInstrInfo.h" #include "PPCSubtarget.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/IR/DataLayout.h" -#include "llvm/Target/TargetMachine.h" #include namespace llvm { /// Common code between 32-bit and 64-bit PowerPC targets. /// -class PPCTargetMachine final : public LLVMTargetMachine { +class PPCTargetMachine final : public CodeGenTargetMachineImpl { public: enum PPCABI { PPC_ABI_UNKNOWN, PPC_ABI_ELFv1, PPC_ABI_ELFv2 }; enum Endian { NOT_DETECTED, LITTLE, BIG }; diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 70035bd0975d0..079850c1774be 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -170,9 +170,9 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT, Options), TT, CPU, FS, Options, - getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT, Options), TT, CPU, FS, + Options, getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()) { initAsmInfo(); diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h index ce7b7907e1f3a..d73447ef273e4 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h @@ -15,13 +15,13 @@ #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "RISCVSubtarget.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/SelectionDAGTargetInfo.h" #include "llvm/IR/DataLayout.h" -#include "llvm/Target/TargetMachine.h" #include namespace llvm { -class RISCVTargetMachine : public LLVMTargetMachine { +class RISCVTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/SPIRV/SPIRVAPI.cpp b/llvm/lib/Target/SPIRV/SPIRVAPI.cpp index a6720d63c63b8..a1ee4aada853b 100644 --- a/llvm/lib/Target/SPIRV/SPIRVAPI.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVAPI.cpp @@ -158,10 +158,9 @@ SPIRVTranslateModule(Module *M, std::string &SpirvObj, std::string &ErrMsg, TargetLibraryInfoImpl TLII(Triple(M->getTargetTriple())); legacy::PassManager PM; PM.add(new TargetLibraryInfoWrapperPass(TLII)); - LLVMTargetMachine &LLVMTM = static_cast(*Target); MachineModuleInfoWrapperPass *MMIWP = - new MachineModuleInfoWrapperPass(&LLVMTM); - const_cast(LLVMTM.getObjFileLowering()) + new MachineModuleInfoWrapperPass(Target.get()); + const_cast(Target->getObjFileLowering()) ->Initialize(MMIWP->getMMI().getContext(), *Target); SmallString<4096> OutBuffer; diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index 194ce7c10bfd3..6646795408fea 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -80,9 +80,9 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()), Subtarget(TT, CPU.str(), FS.str(), *this) { initAsmInfo(); diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h index a1a9f26846153..3ea0f671ff6d8 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h @@ -14,11 +14,11 @@ #define LLVM_LIB_TARGET_SPIRV_SPIRVTARGETMACHINE_H #include "SPIRVSubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { -class SPIRVTargetMachine : public LLVMTargetMachine { +class SPIRVTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; SPIRVSubtarget Subtarget; diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 50a96368bbdca..abbd56a41d9ca 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -107,11 +107,12 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT, std::optional CM, CodeGenOptLevel OL, bool JIT, bool is64bit) - : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), - getEffectiveSparcCodeModel( - CM, getEffectiveRelocModel(RM), is64bit, JIT), - OL), + : CodeGenTargetMachineImpl( + T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), + getEffectiveSparcCodeModel(CM, getEffectiveRelocModel(RM), is64bit, + JIT), + OL), TLOF(std::make_unique()), is64Bit(is64bit) { initAsmInfo(); } diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h index 497d5f6623cd3..9a226a47671b3 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.h +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h @@ -15,12 +15,13 @@ #include "SparcInstrInfo.h" #include "SparcSubtarget.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/Target/TargetMachine.h" #include namespace llvm { -class SparcTargetMachine : public LLVMTargetMachine { +class SparcTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; bool is64Bit; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index f76f41768e886..9000df2f6be0f 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -158,7 +158,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine( + : CodeGenTargetMachineImpl( T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(RM), getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT), diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h index 75e5d68e74eef..75b622046a630 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h @@ -17,6 +17,7 @@ #include "SystemZSubtarget.h" #include "llvm/ADT/StringRef.h" #include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/Support/CodeGen.h" #include "llvm/Target/TargetMachine.h" #include @@ -24,7 +25,7 @@ namespace llvm { -class SystemZTargetMachine : public LLVMTargetMachine { +class SystemZTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp index 383667bf79e1b..3a6f73cc697e6 100644 --- a/llvm/lib/Target/VE/VETargetMachine.cpp +++ b/llvm/lib/Target/VE/VETargetMachine.cpp @@ -89,9 +89,9 @@ VETargetMachine::VETargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(createTLOF()), Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); diff --git a/llvm/lib/Target/VE/VETargetMachine.h b/llvm/lib/Target/VE/VETargetMachine.h index fd838296b9dd0..540d5d8e712a1 100644 --- a/llvm/lib/Target/VE/VETargetMachine.h +++ b/llvm/lib/Target/VE/VETargetMachine.h @@ -15,12 +15,12 @@ #include "VEInstrInfo.h" #include "VESubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { -class VETargetMachine : public LLVMTargetMachine { +class VETargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; VESubtarget Subtarget; // Hold Strings that can be free'd all together with VETargetMachine diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp index 9d43c0052d52e..a23f52b8aa907 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp @@ -47,9 +47,9 @@ WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo(const Triple &T, // When compilation is done on a cpp file by clang, the exception model info // is stored in LangOptions, which is later used to set the info in - // TargetOptions and then MCAsmInfo in LLVMTargetMachine::initAsmInfo(). But - // this process does not happen when compiling bitcode directly with clang, so - // we make sure this info is set correctly. + // TargetOptions and then MCAsmInfo in CodeGenTargetMachine::initAsmInfo(). + // But this process does not happen when compiling bitcode directly with + // clang, so we make sure this info is set correctly. if (WebAssembly::WasmEnableEH || WebAssembly::WasmEnableSjLj) ExceptionsType = ExceptionHandling::Wasm; } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index 83cd57d0bbdd5..75a124a304d66 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -115,7 +115,7 @@ WebAssemblyTargetMachine::WebAssemblyTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine( + : CodeGenTargetMachineImpl( T, TT.isArch64Bit() ? (TT.isOSEmscripten() ? "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-" diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h index 1ff2e175978c3..1d8197d02588a 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h @@ -16,12 +16,12 @@ #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYTARGETMACHINE_H #include "WebAssemblySubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { -class WebAssemblyTargetMachine final : public LLVMTargetMachine { +class WebAssemblyTargetMachine final : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; bool UsesMultivalueABI = false; diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 9f58404c351c2..20dfdd27b33df 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -233,11 +233,9 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine( - T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(TT, JIT, RM), - getEffectiveX86CodeModel(TT, CM, JIT), - OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(TT, JIT, RM), + getEffectiveX86CodeModel(TT, CM, JIT), OL), TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) { // On PS4/PS5, the "return address" of a 'noreturn' call must still be within // the calling function. Note that this also includes __stack_chk_fail, diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index d27c8a4d10116..b8d84a8d20032 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -15,8 +15,8 @@ #include "X86Subtarget.h" #include "llvm/ADT/StringMap.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/Support/CodeGen.h" -#include "llvm/Target/TargetMachine.h" #include #include @@ -25,7 +25,7 @@ namespace llvm { class StringRef; class TargetTransformInfo; -class X86TargetMachine final : public LLVMTargetMachine { +class X86TargetMachine final : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; // True if this is used in JIT. diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index bb5beefbb65e1..64582ea963ee2 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -48,7 +48,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine( + : CodeGenTargetMachineImpl( T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32", TT, CPU, FS, Options, getEffectiveRelocModel(RM), getEffectiveXCoreCodeModel(CM), OL), diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.h b/llvm/lib/Target/XCore/XCoreTargetMachine.h index 23276935713b6..b844e7ea76f06 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.h +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.h @@ -15,15 +15,15 @@ #include "XCoreSubtarget.h" #include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/Support/CodeGen.h" -#include "llvm/Target/TargetMachine.h" #include #include namespace llvm { class StringRef; -class XCoreTargetMachine : public LLVMTargetMachine { +class XCoreTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; XCoreSubtarget Subtarget; diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 8bbb2156e2690..7fb998d615c46 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -50,9 +50,9 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT, std::optional CM, CodeGenOptLevel OL, bool JIT, bool IsLittle) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT, - CPU, FS, Options, getEffectiveRelocModel(JIT, RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenCommonTMImpl(T, computeDataLayout(TT, CPU, Options, IsLittle), TT, + CPU, FS, Options, getEffectiveRelocModel(JIT, RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()) { initAsmInfo(); } diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h index 6975076b5d699..ada42f31a11b2 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h @@ -16,13 +16,13 @@ #define LLVM_LIB_TARGET_XTENSA_XTENSATARGETMACHINE_H #include "XtensaSubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include namespace llvm { extern Target TheXtensaTarget; -class XtensaTargetMachine : public LLVMTargetMachine { +class XtensaTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr TLOF; public: XtensaTargetMachine(const Target &T, const Triple &TT, StringRef CPU, diff --git a/llvm/tools/llc/NewPMDriver.cpp b/llvm/tools/llc/NewPMDriver.cpp index 2a49eaff1d7cb..3892fbb8c74f7 100644 --- a/llvm/tools/llc/NewPMDriver.cpp +++ b/llvm/tools/llc/NewPMDriver.cpp @@ -99,8 +99,6 @@ int llvm::compileModuleWithNewPM( return 1; } - LLVMTargetMachine &LLVMTM = static_cast(*Target); - raw_pwrite_stream *OS = &Out->os(); // Fetch options from TargetPassConfig @@ -109,12 +107,12 @@ int llvm::compileModuleWithNewPM( Opt.DebugPM = DebugPM; Opt.RegAlloc = RegAlloc; - MachineModuleInfo MMI(&LLVMTM); + MachineModuleInfo MMI(Target.get()); PassInstrumentationCallbacks PIC; StandardInstrumentations SI(Context, Opt.DebugPM, VK == VerifierKind::EachPass); - registerCodeGenCallback(PIC, LLVMTM); + registerCodeGenCallback(PIC, *Target); MachineFunctionAnalysisManager MFAM; LoopAnalysisManager LAM; @@ -158,7 +156,7 @@ int llvm::compileModuleWithNewPM( if (MIR->parseMachineFunctions(*M, MAM)) return 1; } else { - ExitOnErr(LLVMTM.buildCodeGenPipeline( + ExitOnErr(Target->buildCodeGenPipeline( MPM, *OS, DwoOut ? &DwoOut->os() : nullptr, FileType, Opt, &PIC)); } diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp index 5bf8ac5cf4181..150dd50ef2936 100644 --- a/llvm/tools/llc/llc.cpp +++ b/llvm/tools/llc/llc.cpp @@ -685,9 +685,8 @@ static int compileModule(char **argv, LLVMContext &Context) { } const char *argv0 = argv[0]; - LLVMTargetMachine &LLVMTM = static_cast(*Target); MachineModuleInfoWrapperPass *MMIWP = - new MachineModuleInfoWrapperPass(&LLVMTM); + new MachineModuleInfoWrapperPass(Target.get()); // Construct a custom pass pipeline that starts after instruction // selection. @@ -698,7 +697,7 @@ static int compileModule(char **argv, LLVMContext &Context) { delete MMIWP; return 1; } - TargetPassConfig *PTPC = LLVMTM.createPassConfig(PM); + TargetPassConfig *PTPC = Target->createPassConfig(PM); TargetPassConfig &TPC = *PTPC; if (TPC.hasLimitedCodeGenPipeline()) { WithColor::warning(errs(), argv[0]) @@ -726,7 +725,7 @@ static int compileModule(char **argv, LLVMContext &Context) { reportError("target does not support generation of this file type"); } - const_cast(LLVMTM.getObjFileLowering()) + const_cast(Target->getObjFileLowering()) ->Initialize(MMIWP->getMMI().getContext(), *Target); if (MIR) { assert(MMIWP && "Forgot to create MMIWP?"); diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp index 92ab3a96d91e6..6f6ef16153b32 100644 --- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp +++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp @@ -232,9 +232,7 @@ createModule(const std::unique_ptr &Context, const DataLayout &DL) BitVector getFunctionReservedRegs(const TargetMachine &TM) { std::unique_ptr Context = std::make_unique(); std::unique_ptr Module = createModule(Context, TM.createDataLayout()); - // TODO: This only works for targets implementing LLVMTargetMachine. - const LLVMTargetMachine &LLVMTM = static_cast(TM); - auto MMIWP = std::make_unique(&LLVMTM); + auto MMIWP = std::make_unique(&TM); MachineFunction &MF = createVoidVoidPtrMachineFunction( FunctionID, Module.get(), &MMIWP->getMMI()); // Saving reserved registers for client. @@ -242,7 +240,7 @@ BitVector getFunctionReservedRegs(const TargetMachine &TM) { } Error assembleToStream(const ExegesisTarget &ET, - std::unique_ptr TM, + std::unique_ptr TM, ArrayRef LiveIns, const FillFunction &Fill, raw_pwrite_stream &AsmStream, const BenchmarkKey &Key, bool GenerateMemoryInstructions) { @@ -358,7 +356,7 @@ object::OwningBinary getObjectFromFile(StringRef Filename) { } Expected ExecutableFunction::create( - std::unique_ptr TM, + std::unique_ptr TM, object::OwningBinary &&ObjectFileHolder) { assert(ObjectFileHolder.getBinary() && "cannot create object file"); std::unique_ptr Ctx = std::make_unique(); diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.h b/llvm/tools/llvm-exegesis/lib/Assembler.h index 198b875446809..4d241e0281b5a 100644 --- a/llvm/tools/llvm-exegesis/lib/Assembler.h +++ b/llvm/tools/llvm-exegesis/lib/Assembler.h @@ -89,7 +89,7 @@ using FillFunction = std::function; // epilogue. Once the MachineFunction is ready, it is assembled for TM to // AsmStream, the temporary function is eventually discarded. Error assembleToStream(const ExegesisTarget &ET, - std::unique_ptr TM, + std::unique_ptr TM, ArrayRef LiveIns, const FillFunction &Fill, raw_pwrite_stream &AsmStreamm, const BenchmarkKey &Key, bool GenerateMemoryInstructions); @@ -107,7 +107,7 @@ object::OwningBinary getObjectFromFile(StringRef Filename); class ExecutableFunction { public: static Expected - create(std::unique_ptr TM, + create(std::unique_ptr TM, object::OwningBinary &&ObjectFileHolder); // Retrieves the function as an array of bytes. diff --git a/llvm/tools/llvm-exegesis/lib/LlvmState.cpp b/llvm/tools/llvm-exegesis/lib/LlvmState.cpp index d453d460abafc..4c44c59286ccf 100644 --- a/llvm/tools/llvm-exegesis/lib/LlvmState.cpp +++ b/llvm/tools/llvm-exegesis/lib/LlvmState.cpp @@ -56,9 +56,8 @@ Expected LLVMState::Create(std::string TripleName, inconvertibleErrorCode()); } const TargetOptions Options; - std::unique_ptr TM( - static_cast(TheTarget->createTargetMachine( - TripleName, CpuName, Features, Options, Reloc::Model::Static))); + std::unique_ptr TM(TheTarget->createTargetMachine( + TripleName, CpuName, Features, Options, Reloc::Model::Static)); if (!TM) { return make_error("unable to create target machine", inconvertibleErrorCode()); @@ -91,13 +90,13 @@ LLVMState::LLVMState(std::unique_ptr TM, IC.reset(new InstructionsCache(getInstrInfo(), getRATC())); } -std::unique_ptr LLVMState::createTargetMachine() const { - return std::unique_ptr(static_cast( +std::unique_ptr LLVMState::createTargetMachine() const { + return std::unique_ptr( TheTargetMachine->getTarget().createTargetMachine( TheTargetMachine->getTargetTriple().normalize(), TheTargetMachine->getTargetCPU(), TheTargetMachine->getTargetFeatureString(), TheTargetMachine->Options, - Reloc::Model::Static))); + Reloc::Model::Static)); } std::optional diff --git a/llvm/tools/llvm-exegesis/lib/LlvmState.h b/llvm/tools/llvm-exegesis/lib/LlvmState.h index f69d76c9a1e4e..761472b2de2a2 100644 --- a/llvm/tools/llvm-exegesis/lib/LlvmState.h +++ b/llvm/tools/llvm-exegesis/lib/LlvmState.h @@ -49,7 +49,7 @@ class LLVMState { bool UseDummyPerfCounters = false); const TargetMachine &getTargetMachine() const { return *TheTargetMachine; } - std::unique_ptr createTargetMachine() const; + std::unique_ptr createTargetMachine() const; const ExegesisTarget &getExegesisTarget() const { return *TheExegesisTarget; } diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp index 5f6a22cb3a974..7cd974f0cf438 100644 --- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp +++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp @@ -521,9 +521,7 @@ ReducerWorkItem::clone(const TargetMachine *TM) const { // MachineModuleInfo contains a lot of other state used during codegen which // we won't be using here, but we should be able to ignore it (although this // is pretty ugly). - const LLVMTargetMachine *LLVMTM = - static_cast(TM); - CloneMMM->MMI = std::make_unique(LLVMTM); + CloneMMM->MMI = std::make_unique(TM); for (const Function &F : getModule()) { if (auto *MF = MMI->getMachineFunction(F)) @@ -839,9 +837,8 @@ llvm::parseReducerWorkItem(StringRef ToolName, StringRef Filename, }; std::unique_ptr M = MParser->parseIRModule(SetDataLayout); - LLVMTargetMachine *LLVMTM = static_cast(TM.get()); - MMM->MMI = std::make_unique(LLVMTM); + MMM->MMI = std::make_unique(TM.get()); MParser->parseMachineFunctions(*M, *MMM->MMI); MMM->M = std::move(M); } else { diff --git a/llvm/tools/opt/optdriver.cpp b/llvm/tools/opt/optdriver.cpp index c5bc7b43e0331..8ef249e1708b9 100644 --- a/llvm/tools/opt/optdriver.cpp +++ b/llvm/tools/opt/optdriver.cpp @@ -801,9 +801,11 @@ extern "C" int optMain( } if (TM) { - // FIXME: We should dyn_cast this when supported. - auto <M = static_cast(*TM); - Pass *TPC = LTM.createPassConfig(Passes); + Pass *TPC = TM->createPassConfig(Passes); + if (!TPC) { + errs() << "Target Machine pass config creation failed.\n"; + return 1; + } Passes.add(TPC); } diff --git a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp index ffedb2c74220f..b00e8dc4424ab 100644 --- a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp +++ b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp @@ -44,9 +44,9 @@ class AArch64SelectionDAGTest : public testing::Test { GTEST_SKIP(); TargetOptions Options; - TM = std::unique_ptr(static_cast( + TM = std::unique_ptr( T->createTargetMachine("AArch64", "", "+sve", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Aggressive))); + std::nullopt, CodeGenOptLevel::Aggressive)); if (!TM) GTEST_SKIP(); @@ -82,7 +82,7 @@ class AArch64SelectionDAGTest : public testing::Test { } LLVMContext Context; - std::unique_ptr TM; + std::unique_ptr TM; std::unique_ptr M; Function *F; std::unique_ptr MF; diff --git a/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp b/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp index ceea57fa10cce..eb86f5dd88989 100644 --- a/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp +++ b/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp @@ -57,9 +57,8 @@ class AMDGPUSelectionDAGTest : public testing::Test { GTEST_SKIP(); TargetOptions Options; - TM = std::unique_ptr( - static_cast(T->createTargetMachine( - "amdgcn--amdpal", "gfx1010", "", Options, std::nullopt))); + TM = std::unique_ptr(T->createTargetMachine( + "amdgcn--amdpal", "gfx1010", "", Options, std::nullopt)); if (!TM) GTEST_SKIP(); @@ -80,7 +79,7 @@ class AMDGPUSelectionDAGTest : public testing::Test { static std::string PalMDString; LLVMContext Context; - std::unique_ptr TM; + std::unique_ptr TM; std::unique_ptr M; SmallString<1024> Elf; }; diff --git a/llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp b/llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp index 1f3d7a55ee854..dc738d85547bb 100644 --- a/llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp +++ b/llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp @@ -398,13 +398,13 @@ class AsmPrinterHandlerTest : public AsmPrinterFixtureBase { auto *AP = TestPrinter->getAP(); AP->addAsmPrinterHandler(std::make_unique(*this)); - LLVMTargetMachine *LLVMTM = static_cast(&AP->TM); + TargetMachine *TM = &AP->TM; legacy::PassManager PM; - PM.add(new MachineModuleInfoWrapperPass(LLVMTM)); + PM.add(new MachineModuleInfoWrapperPass(TM)); PM.add(TestPrinter->releaseAP()); // Takes ownership of destroying AP LLVMContext Context; std::unique_ptr M(new Module("TestModule", Context)); - M->setDataLayout(LLVMTM->createDataLayout()); + M->setDataLayout(TM->createDataLayout()); PM.run(*M); // Now check that we can run it twice. AP->addAsmPrinterHandler(std::make_unique(*this)); @@ -448,13 +448,13 @@ class AsmPrinterDebugHandlerTest : public AsmPrinterFixtureBase { auto *AP = TestPrinter->getAP(); AP->addDebugHandler(std::make_unique(*this, AP)); - LLVMTargetMachine *LLVMTM = static_cast(&AP->TM); + TargetMachine *TM = &AP->TM; legacy::PassManager PM; - PM.add(new MachineModuleInfoWrapperPass(LLVMTM)); + PM.add(new MachineModuleInfoWrapperPass(TM)); PM.add(TestPrinter->releaseAP()); // Takes ownership of destroying AP LLVMContext Context; std::unique_ptr M(new Module("TestModule", Context)); - M->setDataLayout(LLVMTM->createDataLayout()); + M->setDataLayout(TM->createDataLayout()); PM.run(*M); // Now check that we can run it twice. AP->addDebugHandler(std::make_unique(*this, AP)); diff --git a/llvm/unittests/CodeGen/CCStateTest.cpp b/llvm/unittests/CodeGen/CCStateTest.cpp index 405e1c6ef90d9..2a1a6130f1ca3 100644 --- a/llvm/unittests/CodeGen/CCStateTest.cpp +++ b/llvm/unittests/CodeGen/CCStateTest.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/TargetFrameLowering.h" @@ -16,7 +17,6 @@ #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/Module.h" #include "llvm/MC/TargetRegistry.h" -#include "llvm/Target/TargetMachine.h" #include "gtest/gtest.h" using namespace llvm; diff --git a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp index b0dbd4a10b0a7..15d2baa24b831 100644 --- a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp @@ -29,8 +29,7 @@ operator<<(std::ostream &OS, const MachineFunction &MF) { } -std::unique_ptr -AArch64GISelMITest::createTargetMachine() const { +std::unique_ptr AArch64GISelMITest::createTargetMachine() const { Triple TargetTriple("aarch64--"); std::string Error; const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error); @@ -38,9 +37,9 @@ AArch64GISelMITest::createTargetMachine() const { return nullptr; TargetOptions Options; - return std::unique_ptr(static_cast( + return std::unique_ptr( T->createTargetMachine("AArch64", "", "", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Aggressive))); + std::nullopt, CodeGenOptLevel::Aggressive)); } void AArch64GISelMITest::getTargetTestModuleString(SmallString<512> &S, @@ -67,8 +66,7 @@ body: | .toNullTerminatedStringRef(S); } -std::unique_ptr -AMDGPUGISelMITest::createTargetMachine() const { +std::unique_ptr AMDGPUGISelMITest::createTargetMachine() const { Triple TargetTriple("amdgcn-amd-amdhsa"); std::string Error; const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error); @@ -76,10 +74,9 @@ AMDGPUGISelMITest::createTargetMachine() const { return nullptr; TargetOptions Options; - return std::unique_ptr(static_cast( - T->createTargetMachine("amdgcn-amd-amdhsa", "gfx900", "", Options, - std::nullopt, std::nullopt, - CodeGenOptLevel::Aggressive))); + return std::unique_ptr(T->createTargetMachine( + "amdgcn-amd-amdhsa", "gfx900", "", Options, std::nullopt, std::nullopt, + CodeGenOptLevel::Aggressive)); } void AMDGPUGISelMITest::getTargetTestModuleString( diff --git a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.h b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.h index 544dcabb56d0a..4b82f572150e5 100644 --- a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.h +++ b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.h @@ -74,7 +74,7 @@ parseMIR(LLVMContext &Context, std::unique_ptr &MIR, return M; } static std::pair, std::unique_ptr> -createDummyModule(LLVMContext &Context, const LLVMTargetMachine &TM, +createDummyModule(LLVMContext &Context, const TargetMachine &TM, StringRef MIRString, const char *FuncName) { std::unique_ptr MIR; auto MMI = std::make_unique(&TM); @@ -102,8 +102,8 @@ class GISelMITest : public ::testing::Test { protected: GISelMITest() : ::testing::Test() {} - /// Prepare a target specific LLVMTargetMachine. - virtual std::unique_ptr createTargetMachine() const = 0; + /// Prepare a target specific TargetMachine. + virtual std::unique_ptr createTargetMachine() const = 0; /// Get the stub sample MIR test function. virtual void getTargetTestModuleString(SmallString<512> &S, @@ -127,7 +127,7 @@ class GISelMITest : public ::testing::Test { } LLVMContext Context; - std::unique_ptr TM; + std::unique_ptr TM; MachineFunction *MF; std::pair, std::unique_ptr> ModuleMMIPair; @@ -138,13 +138,13 @@ class GISelMITest : public ::testing::Test { }; class AArch64GISelMITest : public GISelMITest { - std::unique_ptr createTargetMachine() const override; + std::unique_ptr createTargetMachine() const override; void getTargetTestModuleString(SmallString<512> &S, StringRef MIRFunc) const override; }; class AMDGPUGISelMITest : public GISelMITest { - std::unique_ptr createTargetMachine() const override; + std::unique_ptr createTargetMachine() const override; void getTargetTestModuleString(SmallString<512> &S, StringRef MIRFunc) const override; }; diff --git a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp index 87f96ed28e326..f943b48f6f4d3 100644 --- a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp +++ b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/MIRParser/MIRParser.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineModuleInfo.h" @@ -21,7 +22,6 @@ #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/TargetSelect.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "../lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h" @@ -90,11 +90,11 @@ class InstrRefLDVTest : public testing::Test { Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &*Mod); unsigned FunctionNum = 42; - MMI = std::make_unique((LLVMTargetMachine *)&*Machine); + MMI = std::make_unique(Machine.get()); const TargetSubtargetInfo &STI = *Machine->getSubtargetImpl(*F); - MF = std::make_unique(*F, (LLVMTargetMachine &)*Machine, - STI, MMI->getContext(), FunctionNum); + MF = std::make_unique(*F, *Machine, STI, MMI->getContext(), + FunctionNum); // Create metadata: CU, subprogram, some blocks and an inline function // scope. diff --git a/llvm/unittests/CodeGen/LexicalScopesTest.cpp b/llvm/unittests/CodeGen/LexicalScopesTest.cpp index 03eca7a06faec..3d707462fa615 100644 --- a/llvm/unittests/CodeGen/LexicalScopesTest.cpp +++ b/llvm/unittests/CodeGen/LexicalScopesTest.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/LexicalScopes.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" @@ -25,7 +26,6 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/TargetSelect.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "gtest/gtest.h" diff --git a/llvm/unittests/CodeGen/MFCommon.inc b/llvm/unittests/CodeGen/MFCommon.inc index 749c5780fbac3..67759bd5c4632 100644 --- a/llvm/unittests/CodeGen/MFCommon.inc +++ b/llvm/unittests/CodeGen/MFCommon.inc @@ -104,12 +104,12 @@ static TargetOptions getTargetOptionsForBogusMachine() { return Opts; } -class BogusTargetMachine : public LLVMTargetMachine { +class BogusTargetMachine : public CodeGenTargetMachineImpl { public: BogusTargetMachine() - : LLVMTargetMachine(Target(), "", Triple(""), "", "", - getTargetOptionsForBogusMachine(), Reloc::Static, - CodeModel::Small, CodeGenOptLevel::Default), + : CodeGenTargetMachineImpl( + Target(), "", Triple(""), "", "", getTargetOptionsForBogusMachine(), + Reloc::Static, CodeModel::Small, CodeGenOptLevel::Default), ST(*this) {} ~BogusTargetMachine() override {} diff --git a/llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp b/llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp index 722ec47646764..00c2c3abf8533 100644 --- a/llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp +++ b/llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp @@ -8,6 +8,7 @@ #include "../../lib/CodeGen/MLRegAllocEvictAdvisor.h" #include "llvm/Analysis/NoInferenceModelRunner.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineModuleInfo.h" @@ -21,7 +22,6 @@ #include "llvm/Support/Allocator.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/TargetSelect.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/TargetParser/Triple.h" #include "gmock/gmock.h" diff --git a/llvm/unittests/CodeGen/MachineBasicBlockTest.cpp b/llvm/unittests/CodeGen/MachineBasicBlockTest.cpp index 25d54e8c80eec..bcb5a18188a8b 100644 --- a/llvm/unittests/CodeGen/MachineBasicBlockTest.cpp +++ b/llvm/unittests/CodeGen/MachineBasicBlockTest.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -20,7 +21,6 @@ #include "llvm/IR/IRBuilder.h" #include "llvm/IR/Module.h" #include "llvm/MC/TargetRegistry.h" -#include "llvm/Target/TargetMachine.h" #include "gmock/gmock.h" #include "gtest/gtest.h" diff --git a/llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp b/llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp index f8505817d2e09..a60c8a2de02c0 100644 --- a/llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp +++ b/llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp @@ -60,8 +60,7 @@ class MachineDomTreeUpdaterTest : public testing::Test { T->createTargetMachine("X86", "", "", Options, std::nullopt)); if (!TM) GTEST_SKIP(); - MMI = std::make_unique( - static_cast(TM.get())); + MMI = std::make_unique(TM.get()); PassBuilder PB(TM.get()); PB.registerModuleAnalyses(MAM); diff --git a/llvm/unittests/CodeGen/MachineInstrTest.cpp b/llvm/unittests/CodeGen/MachineInstrTest.cpp index a3856f4bf9270..c32c2ce859af5 100644 --- a/llvm/unittests/CodeGen/MachineInstrTest.cpp +++ b/llvm/unittests/CodeGen/MachineInstrTest.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -25,7 +26,6 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/TargetSelect.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/TargetParser/Triple.h" #include "gmock/gmock.h" diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp index 63059d3267f71..714d6b5c50265 100644 --- a/llvm/unittests/CodeGen/MachineOperandTest.cpp +++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp @@ -8,6 +8,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/ADT/ilist_node.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/TargetFrameLowering.h" @@ -23,7 +24,6 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetMachine.h" #include "gtest/gtest.h" using namespace llvm; diff --git a/llvm/unittests/CodeGen/PassManagerTest.cpp b/llvm/unittests/CodeGen/PassManagerTest.cpp index d3a410f5450cc..5e20c8db56fa8 100644 --- a/llvm/unittests/CodeGen/PassManagerTest.cpp +++ b/llvm/unittests/CodeGen/PassManagerTest.cpp @@ -179,10 +179,9 @@ TEST_F(PassManagerTest, Basic) { if (!TM) GTEST_SKIP(); - LLVMTargetMachine *LLVMTM = static_cast(TM.get()); M->setDataLayout(TM->createDataLayout()); - MachineModuleInfo MMI(LLVMTM); + MachineModuleInfo MMI(TM.get()); MachineFunctionAnalysisManager MFAM; LoopAnalysisManager LAM; @@ -229,10 +228,9 @@ TEST_F(PassManagerTest, DiagnosticHandler) { if (!TM) GTEST_SKIP(); - LLVMTargetMachine *LLVMTM = static_cast(TM.get()); M->setDataLayout(TM->createDataLayout()); - MachineModuleInfo MMI(LLVMTM); + MachineModuleInfo MMI(TM.get()); LoopAnalysisManager LAM; MachineFunctionAnalysisManager MFAM; diff --git a/llvm/unittests/CodeGen/RegAllocScoreTest.cpp b/llvm/unittests/CodeGen/RegAllocScoreTest.cpp index 9f8576eb7312b..f823f363b1e31 100644 --- a/llvm/unittests/CodeGen/RegAllocScoreTest.cpp +++ b/llvm/unittests/CodeGen/RegAllocScoreTest.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "../lib/CodeGen/RegAllocScore.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" @@ -24,7 +25,6 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/TargetSelect.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/TargetParser/Triple.h" #include "gtest/gtest.h" diff --git a/llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp b/llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp index c89e5a45ab014..1958104720644 100644 --- a/llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp +++ b/llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp @@ -47,9 +47,9 @@ class SelectionDAGAddressAnalysisTest : public testing::Test { GTEST_SKIP(); TargetOptions Options; - TM = std::unique_ptr(static_cast( + TM = std::unique_ptr( T->createTargetMachine("AArch64", "", "+sve", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Aggressive))); + std::nullopt, CodeGenOptLevel::Aggressive)); if (!TM) GTEST_SKIP(); @@ -91,7 +91,7 @@ class SelectionDAGAddressAnalysisTest : public testing::Test { } LLVMContext Context; - std::unique_ptr TM; + std::unique_ptr TM; std::unique_ptr M; Function *F; GlobalVariable *G; diff --git a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp index 1402c1d5b1398..b9bcb2479fdcc 100644 --- a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp +++ b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp @@ -45,10 +45,9 @@ class SelectionDAGPatternMatchTest : public testing::Test { GTEST_SKIP(); TargetOptions Options; - TM = std::unique_ptr(static_cast( - T->createTargetMachine("riscv64", "", "+m,+f,+d,+v", Options, - std::nullopt, std::nullopt, - CodeGenOptLevel::Aggressive))); + TM = std::unique_ptr(T->createTargetMachine( + "riscv64", "", "+m,+f,+d,+v", Options, std::nullopt, std::nullopt, + CodeGenOptLevel::Aggressive)); if (!TM) GTEST_SKIP(); @@ -90,7 +89,7 @@ class SelectionDAGPatternMatchTest : public testing::Test { } LLVMContext Context; - std::unique_ptr TM; + std::unique_ptr TM; std::unique_ptr M; Function *F; GlobalVariable *G; diff --git a/llvm/unittests/CodeGen/TargetOptionsTest.cpp b/llvm/unittests/CodeGen/TargetOptionsTest.cpp index 2105427e55012..b8b6eaefceff9 100644 --- a/llvm/unittests/CodeGen/TargetOptionsTest.cpp +++ b/llvm/unittests/CodeGen/TargetOptionsTest.cpp @@ -51,9 +51,8 @@ static void targetOptionsTest(bool EnableIPRA) { if (!TM) GTEST_SKIP(); legacy::PassManager PM; - LLVMTargetMachine *LLVMTM = static_cast(TM.get()); - TargetPassConfig *TPC = LLVMTM->createPassConfig(PM); + TargetPassConfig *TPC = TM->createPassConfig(PM); (void)TPC; ASSERT_TRUE(TM->Options.EnableIPRA == EnableIPRA); diff --git a/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp b/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp index 7f7a3720cf7ce..a0c843711a219 100644 --- a/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp +++ b/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp @@ -27,7 +27,7 @@ void InitializeAMDGPUTarget() { }); } -std::unique_ptr +std::unique_ptr createTargetMachine(std::string TStr, StringRef CPU, StringRef FS) { InitializeAMDGPUTarget(); @@ -37,9 +37,8 @@ createTargetMachine(std::string TStr, StringRef CPU, StringRef FS) { return nullptr; TargetOptions Options; - return std::unique_ptr( - static_cast(T->createTargetMachine( - TStr, CPU, FS, Options, std::nullopt, std::nullopt))); + return std::unique_ptr(T->createTargetMachine( + TStr, CPU, FS, Options, std::nullopt, std::nullopt)); } TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) { diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp index f910e8e1f2c8f..cd3307598de52 100644 --- a/llvm/unittests/MI/LiveIntervalTest.cpp +++ b/llvm/unittests/MI/LiveIntervalTest.cpp @@ -41,7 +41,7 @@ void initLLVM() { /// Create a TargetMachine. As we lack a dedicated always available target for /// unittests, we go for "AMDGPU" to be able to test normal and subregister /// liveranges. -std::unique_ptr createTargetMachine() { +std::unique_ptr createTargetMachine() { Triple TargetTriple("amdgcn--"); std::string Error; const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error); @@ -49,16 +49,15 @@ std::unique_ptr createTargetMachine() { return nullptr; TargetOptions Options; - return std::unique_ptr(static_cast( + return std::unique_ptr( T->createTargetMachine("AMDGPU", "gfx900", "", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Aggressive))); + std::nullopt, CodeGenOptLevel::Aggressive)); } std::unique_ptr parseMIR(LLVMContext &Context, legacy::PassManagerBase &PM, std::unique_ptr &MIR, - const LLVMTargetMachine &TM, - StringRef MIRCode) { + const TargetMachine &TM, StringRef MIRCode) { SMDiagnostic Diagnostic; std::unique_ptr MBuffer = MemoryBuffer::getMemBuffer(MIRCode); MIR = createMIRParser(std::move(MBuffer), Context); @@ -206,7 +205,7 @@ static void doTest(StringRef MIRFunc, typename TestPassT::TestFx T, bool ShouldPass = true) { LLVMContext Context; - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); // This test is designed for the X86 backend; stop if it is not available. if (!TM) return; diff --git a/llvm/unittests/MIR/MachineMetadata.cpp b/llvm/unittests/MIR/MachineMetadata.cpp index ac1397f4ba645..b16f70be6efe5 100644 --- a/llvm/unittests/MIR/MachineMetadata.cpp +++ b/llvm/unittests/MIR/MachineMetadata.cpp @@ -66,16 +66,15 @@ class MachineMetadataTest : public testing::Test { }); } - std::unique_ptr + std::unique_ptr createTargetMachine(std::string TT, StringRef CPU, StringRef FS) { std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) return nullptr; TargetOptions Options; - return std::unique_ptr( - static_cast(T->createTargetMachine( - TT, CPU, FS, Options, std::nullopt, std::nullopt))); + return std::unique_ptr(T->createTargetMachine( + TT, CPU, FS, Options, std::nullopt, std::nullopt)); } std::unique_ptr parseMIR(const TargetMachine &TM, StringRef MIRCode, diff --git a/llvm/unittests/MIR/MachineStableHashTest.cpp b/llvm/unittests/MIR/MachineStableHashTest.cpp index 1d888c2ec3e72..5ba391f0daf7a 100644 --- a/llvm/unittests/MIR/MachineStableHashTest.cpp +++ b/llvm/unittests/MIR/MachineStableHashTest.cpp @@ -37,16 +37,15 @@ class MachineStableHashTest : public testing::Test { void SetUp() override { M = std::make_unique("Dummy", Context); } - std::unique_ptr + std::unique_ptr createTargetMachine(std::string TT, StringRef CPU, StringRef FS) { std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) return nullptr; TargetOptions Options; - return std::unique_ptr( - static_cast(T->createTargetMachine( - TT, CPU, FS, Options, std::nullopt, std::nullopt))); + return std::unique_ptr(T->createTargetMachine( + TT, CPU, FS, Options, std::nullopt, std::nullopt)); } std::unique_ptr parseMIR(const TargetMachine &TM, StringRef MIRCode, diff --git a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp index aff32d6f7a30b..00e221eb43467 100644 --- a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp +++ b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp @@ -18,7 +18,7 @@ using namespace llvm; namespace { -std::unique_ptr createTargetMachine(const std::string &CPU) { +std::unique_ptr createTargetMachine(const std::string &CPU) { auto TT(Triple::normalize("aarch64--")); LLVMInitializeAArch64TargetInfo(); @@ -28,9 +28,9 @@ std::unique_ptr createTargetMachine(const std::string &CPU) { std::string Error; const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); - return std::unique_ptr(static_cast( + return std::unique_ptr( TheTarget->createTargetMachine(TT, CPU, "", TargetOptions(), std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); } std::unique_ptr createInstrInfo(TargetMachine *TM) { @@ -41,7 +41,7 @@ std::unique_ptr createInstrInfo(TargetMachine *TM) { } TEST(AArch64LaneBitmasks, SubRegs) { - std::unique_ptr TM = createTargetMachine(""); + std::unique_ptr TM = createTargetMachine(""); ASSERT_TRUE(TM); std::unique_ptr II = createInstrInfo(TM.get()); diff --git a/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp b/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp index 08b9eb5d452b7..5dd03ac07334a 100644 --- a/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp +++ b/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp @@ -15,7 +15,7 @@ using namespace llvm; namespace { -std::unique_ptr createTargetMachine(const std::string &CPU) { +std::unique_ptr createTargetMachine(const std::string &CPU) { auto TT(Triple::normalize("aarch64--")); LLVMInitializeAArch64TargetInfo(); @@ -25,9 +25,9 @@ std::unique_ptr createTargetMachine(const std::string &CPU) { std::string Error; const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); - return std::unique_ptr(static_cast( + return std::unique_ptr( TheTarget->createTargetMachine(TT, CPU, "", TargetOptions(), std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); } std::unique_ptr createInstrInfo(TargetMachine *TM) { @@ -52,7 +52,7 @@ static bool isInstructionSupportedByCPU(unsigned Opcode, void runSVEPseudoTestForCPU(const std::string &CPU) { - std::unique_ptr TM = createTargetMachine(CPU); + std::unique_ptr TM = createTargetMachine(CPU); ASSERT_TRUE(TM); std::unique_ptr II = createInstrInfo(TM.get()); ASSERT_TRUE(II); diff --git a/llvm/unittests/Target/AArch64/InstSizes.cpp b/llvm/unittests/Target/AArch64/InstSizes.cpp index 1308d8b19637c..87619dbc34851 100644 --- a/llvm/unittests/Target/AArch64/InstSizes.cpp +++ b/llvm/unittests/Target/AArch64/InstSizes.cpp @@ -12,7 +12,7 @@ using namespace llvm; namespace { -std::unique_ptr createTargetMachine() { +std::unique_ptr createTargetMachine() { auto TT(Triple::normalize("aarch64--")); std::string CPU("generic"); std::string FS("+pauth,+mops,+mte"); @@ -24,9 +24,9 @@ std::unique_ptr createTargetMachine() { std::string Error; const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); - return std::unique_ptr(static_cast( + return std::unique_ptr( TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); } std::unique_ptr createInstrInfo(TargetMachine *TM) { @@ -42,7 +42,7 @@ std::unique_ptr createInstrInfo(TargetMachine *TM) { /// TODO: Some of this might be useful for other architectures as well - extract /// the platform-independent parts somewhere they can be reused. void runChecks( - LLVMTargetMachine *TM, AArch64InstrInfo *II, const StringRef InputIRSnippet, + TargetMachine *TM, AArch64InstrInfo *II, const StringRef InputIRSnippet, const StringRef InputMIRSnippet, std::function Checks) { LLVMContext Context; @@ -88,7 +88,7 @@ void runChecks( } // anonymous namespace TEST(InstSizes, Authenticated) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); ASSERT_TRUE(TM); std::unique_ptr II = createInstrInfo(TM.get()); @@ -120,7 +120,7 @@ TEST(InstSizes, Authenticated) { } TEST(InstSizes, STACKMAP) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); ASSERT_TRUE(TM); std::unique_ptr II = createInstrInfo(TM.get()); @@ -135,7 +135,7 @@ TEST(InstSizes, STACKMAP) { } TEST(InstSizes, PATCHPOINT) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks(TM.get(), II.get(), "", @@ -150,7 +150,7 @@ TEST(InstSizes, PATCHPOINT) { } TEST(InstSizes, STATEPOINT) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks(TM.get(), II.get(), "", @@ -163,7 +163,7 @@ TEST(InstSizes, STATEPOINT) { } TEST(InstSizes, SPACE) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks(TM.get(), II.get(), "", @@ -178,7 +178,7 @@ TEST(InstSizes, SPACE) { } TEST(InstSizes, TLSDESC_CALLSEQ) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks( @@ -192,7 +192,7 @@ TEST(InstSizes, TLSDESC_CALLSEQ) { } TEST(InstSizes, StoreSwiftAsyncContext) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks( @@ -206,7 +206,7 @@ TEST(InstSizes, StoreSwiftAsyncContext) { } TEST(InstSizes, SpeculationBarrierISBDSBEndBB) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks( @@ -220,7 +220,7 @@ TEST(InstSizes, SpeculationBarrierISBDSBEndBB) { } TEST(InstSizes, SpeculationBarrierSBEndBB) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks( @@ -234,7 +234,7 @@ TEST(InstSizes, SpeculationBarrierSBEndBB) { } TEST(InstSizes, JumpTable) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks(TM.get(), II.get(), "", @@ -252,7 +252,7 @@ TEST(InstSizes, JumpTable) { } TEST(InstSizes, MOPSMemoryPseudos) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks(TM.get(), II.get(), "", diff --git a/llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp b/llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp index ebd49be989921..d5823660cf8cc 100644 --- a/llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp +++ b/llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp @@ -7,7 +7,7 @@ using namespace llvm; namespace { -std::unique_ptr createTargetMachine() { +std::unique_ptr createTargetMachine() { auto TT(Triple::normalize("aarch64--")); std::string CPU("generic"); std::string FS("+sme"); @@ -19,9 +19,9 @@ std::unique_ptr createTargetMachine() { std::string Error; const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); - return std::unique_ptr(static_cast( + return std::unique_ptr( TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); } std::unique_ptr createInstrInfo(TargetMachine *TM) { @@ -33,7 +33,7 @@ std::unique_ptr createInstrInfo(TargetMachine *TM) { } TEST(MatrixRegisterAliasing, Aliasing) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); ASSERT_TRUE(TM); std::unique_ptr II = createInstrInfo(TM.get()); diff --git a/llvm/unittests/Target/ARM/InstSizes.cpp b/llvm/unittests/Target/ARM/InstSizes.cpp index 082bd12e52f4c..8b743f155dee6 100644 --- a/llvm/unittests/Target/ARM/InstSizes.cpp +++ b/llvm/unittests/Target/ARM/InstSizes.cpp @@ -18,7 +18,7 @@ namespace { /// TODO: Some of this might be useful for other architectures as well - extract /// the platform-independent parts somewhere they can be reused. void runChecks( - LLVMTargetMachine *TM, const ARMBaseInstrInfo *II, + TargetMachine *TM, const ARMBaseInstrInfo *II, const StringRef InputIRSnippet, const StringRef InputMIRSnippet, unsigned Expected, std::function @@ -82,9 +82,9 @@ TEST(InstSizes, PseudoInst) { } TargetOptions Options; - auto TM = std::unique_ptr(static_cast( + auto TM = std::unique_ptr( T->createTargetMachine(TT, "generic", "", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), std::string(TM->getTargetFeatureString()), *static_cast(TM.get()), false); diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp index 3a76054ca4f36..9d844b3bfaa3c 100644 --- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp +++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp @@ -83,9 +83,9 @@ TEST(MachineInstructionDoubleWidthResult, IsCorrect) { } TargetOptions Options; - auto TM = std::unique_ptr(static_cast( + auto TM = std::unique_ptr( T->createTargetMachine(TT, "generic", "", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), std::string(TM->getTargetFeatureString()), *static_cast(TM.get()), false); @@ -239,9 +239,9 @@ TEST(MachineInstructionHorizontalReduction, IsCorrect) { } TargetOptions Options; - auto TM = std::unique_ptr(static_cast( + auto TM = std::unique_ptr( T->createTargetMachine(TT, "generic", "", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), std::string(TM->getTargetFeatureString()), *static_cast(TM.get()), false); @@ -338,9 +338,9 @@ TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) { } TargetOptions Options; - auto TM = std::unique_ptr(static_cast( + auto TM = std::unique_ptr( T->createTargetMachine(TT, "generic", "", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), std::string(TM->getTargetFeatureString()), *static_cast(TM.get()), false); @@ -1044,9 +1044,9 @@ TEST(MachineInstrValidTailPredication, IsCorrect) { } TargetOptions Options; - auto TM = std::unique_ptr(static_cast( + auto TM = std::unique_ptr( T->createTargetMachine(TT, "generic", "", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), std::string(TM->getTargetFeatureString()), *static_cast(TM.get()), false); @@ -1187,9 +1187,9 @@ TEST(MachineInstr, HasSideEffects) { } TargetOptions Options; - auto TM = std::unique_ptr(static_cast( + auto TM = std::unique_ptr( T->createTargetMachine(TT, "generic", "", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), std::string(TM->getTargetFeatureString()), *static_cast(TM.get()), false); @@ -2067,9 +2067,9 @@ TEST(MachineInstr, MVEVecSize) { } TargetOptions Options; - auto TM = std::unique_ptr(static_cast( + auto TM = std::unique_ptr( T->createTargetMachine(TT, "generic", "", Options, std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), std::string(TM->getTargetFeatureString()), *static_cast(TM.get()), false); diff --git a/llvm/unittests/Target/LoongArch/InstSizes.cpp b/llvm/unittests/Target/LoongArch/InstSizes.cpp index 2a0e9e20f7243..4a679707fc0f1 100644 --- a/llvm/unittests/Target/LoongArch/InstSizes.cpp +++ b/llvm/unittests/Target/LoongArch/InstSizes.cpp @@ -13,7 +13,7 @@ using namespace llvm; namespace { -std::unique_ptr createTargetMachine() { +std::unique_ptr createTargetMachine() { auto TT(Triple::normalize("loongarch64--")); std::string CPU("generic-la64"); std::string FS("+64bit"); @@ -25,9 +25,9 @@ std::unique_ptr createTargetMachine() { std::string Error; const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); - return std::unique_ptr(static_cast( + return std::unique_ptr( TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); } std::unique_ptr createInstrInfo(TargetMachine *TM) { @@ -42,8 +42,8 @@ std::unique_ptr createInstrInfo(TargetMachine *TM) { /// the \p InputMIRSnippet (global variables etc) /// Inspired by AArch64 void runChecks( - LLVMTargetMachine *TM, LoongArchInstrInfo *II, - const StringRef InputIRSnippet, const StringRef InputMIRSnippet, + TargetMachine *TM, LoongArchInstrInfo *II, const StringRef InputIRSnippet, + const StringRef InputMIRSnippet, std::function Checks) { LLVMContext Context; @@ -87,7 +87,7 @@ void runChecks( } // anonymous namespace TEST(InstSizes, INLINEASM_BR) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks(TM.get(), II.get(), "", @@ -101,7 +101,7 @@ TEST(InstSizes, INLINEASM_BR) { } TEST(InstSizes, SPACE) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks(TM.get(), II.get(), "", " INLINEASM &\".space 1024\", 1\n", @@ -112,7 +112,7 @@ TEST(InstSizes, SPACE) { } TEST(InstSizes, AtomicPseudo) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks( @@ -142,7 +142,7 @@ TEST(InstSizes, AtomicPseudo) { } TEST(InstSizes, StatePoint) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); std::unique_ptr II = createInstrInfo(TM.get()); runChecks( diff --git a/llvm/unittests/Target/VE/MachineInstrTest.cpp b/llvm/unittests/Target/VE/MachineInstrTest.cpp index 05b81b6fccfcf..d8e7cc7b60112 100644 --- a/llvm/unittests/Target/VE/MachineInstrTest.cpp +++ b/llvm/unittests/Target/VE/MachineInstrTest.cpp @@ -290,10 +290,9 @@ TEST(VETest, VLIndex) { } TargetOptions Options; - auto TM = std::unique_ptr( - static_cast( + auto TM = std::unique_ptr( T->createTargetMachine(TT, "", "", Options, std::nullopt, std::nullopt, - CodeGenOptLevel::Default))); + CodeGenOptLevel::Default)); VESubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), std::string(TM->getTargetFeatureString()), *static_cast(TM.get())); diff --git a/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp b/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp index 073beb9446ffb..9bbbb352efdce 100644 --- a/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp +++ b/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp @@ -22,7 +22,7 @@ using namespace llvm; namespace { -std::unique_ptr createTargetMachine() { +std::unique_ptr createTargetMachine() { auto TT(Triple::normalize("wasm32-unknown-unknown")); std::string CPU; std::string FS; @@ -35,9 +35,9 @@ std::unique_ptr createTargetMachine() { const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); assert(TheTarget); - return std::unique_ptr(static_cast( + return std::unique_ptr( TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); } std::unique_ptr parseMIR(LLVMContext &Context, @@ -65,7 +65,7 @@ std::unique_ptr parseMIR(LLVMContext &Context, } // namespace TEST(WebAssemblyExceptionInfoTest, TEST0) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); ASSERT_TRUE(TM); StringRef MIRString = R"MIR( @@ -227,7 +227,7 @@ body: | } TEST(WebAssemblyExceptionInfoTest, TEST1) { - std::unique_ptr TM = createTargetMachine(); + std::unique_ptr TM = createTargetMachine(); ASSERT_TRUE(TM); StringRef MIRString = R"MIR( diff --git a/llvm/unittests/Target/X86/MachineSizeOptsTest.cpp b/llvm/unittests/Target/X86/MachineSizeOptsTest.cpp index f4dab399803d1..d7f430b629460 100644 --- a/llvm/unittests/Target/X86/MachineSizeOptsTest.cpp +++ b/llvm/unittests/Target/X86/MachineSizeOptsTest.cpp @@ -28,20 +28,20 @@ using namespace llvm; namespace { -std::unique_ptr createTargetMachine() { +std::unique_ptr createTargetMachine() { auto TT(Triple::normalize("x86_64--")); std::string Error; const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); - return std::unique_ptr(static_cast( + return std::unique_ptr( TheTarget->createTargetMachine(TT, "", "", TargetOptions(), std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); } class MachineSizeOptsTest : public testing::Test { protected: static const char* MIRString; LLVMContext Context; - std::unique_ptr TM; + std::unique_ptr TM; std::unique_ptr MMI; std::unique_ptr Parser; std::unique_ptr M; diff --git a/llvm/unittests/Target/X86/TernlogTest.cpp b/llvm/unittests/Target/X86/TernlogTest.cpp index 34bd0b1fc543a..edb4431a05a68 100644 --- a/llvm/unittests/Target/X86/TernlogTest.cpp +++ b/llvm/unittests/Target/X86/TernlogTest.cpp @@ -20,7 +20,7 @@ #include namespace llvm { -static std::unique_ptr initTM() { +static std::unique_ptr initTM() { LLVMInitializeX86TargetInfo(); LLVMInitializeX86Target(); LLVMInitializeX86TargetMC(); @@ -28,9 +28,9 @@ static std::unique_ptr initTM() { auto TT(Triple::normalize("x86_64--")); std::string Error; const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); - return std::unique_ptr(static_cast( + return std::unique_ptr( TheTarget->createTargetMachine(TT, "", "", TargetOptions(), std::nullopt, - std::nullopt, CodeGenOptLevel::Default))); + std::nullopt, CodeGenOptLevel::Default)); } struct TernTester { diff --git a/llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h b/llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h index 9cf63931e6dd5..985f6f802e4ad 100644 --- a/llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h +++ b/llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h @@ -61,7 +61,7 @@ class MachineFunctionGeneratorBaseTest : public ::testing::Test { } private: - std::unique_ptr createTargetMachine() { + std::unique_ptr createTargetMachine() { std::string Error; const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); EXPECT_TRUE(TheTarget) << Error << " " << TT; @@ -69,8 +69,7 @@ class MachineFunctionGeneratorBaseTest : public ::testing::Test { TargetMachine *TM = TheTarget->createTargetMachine(TT, CpuName, "", Options, Reloc::Model::Static); EXPECT_TRUE(TM) << TT << " " << CpuName; - return std::unique_ptr( - static_cast(TM)); + return std::unique_ptr(TM); } ExecutableFunction diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp index b55ca5057ae01..41ee4028051bb 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp @@ -55,7 +55,7 @@ class X86SnippetRepetitorTest : public X86TestBase { static constexpr const unsigned kMinInstructions = 3; static constexpr const unsigned kLoopBodySize = 5; - std::unique_ptr TM; + std::unique_ptr TM; std::unique_ptr Context; std::unique_ptr Mod; std::unique_ptr MMI; diff --git a/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn index 9eae4b9f69eec..59ecb66f2bcb0 100644 --- a/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn @@ -83,7 +83,7 @@ static_library("CodeGen") { "IntrinsicLowering.cpp", "JMCInstrumenter.cpp", "KCFI.cpp", - "LLVMTargetMachine.cpp", + "CodeGenTargetMachineImpl.cpp", "LatencyPriorityQueue.cpp", "LazyMachineBlockFrequencyInfo.cpp", "LexicalScopes.cpp", diff --git a/offload/plugins-nextgen/common/src/JIT.cpp b/offload/plugins-nextgen/common/src/JIT.cpp index 9adb62b677b92..423dae3957d41 100644 --- a/offload/plugins-nextgen/common/src/JIT.cpp +++ b/offload/plugins-nextgen/common/src/JIT.cpp @@ -175,8 +175,7 @@ void JITEngine::codegen(TargetMachine *TM, TargetLibraryInfoImpl *TLII, Module &M, raw_pwrite_stream &OS) { legacy::PassManager PM; PM.add(new TargetLibraryInfoWrapperPass(*TLII)); - MachineModuleInfoWrapperPass *MMIWP = new MachineModuleInfoWrapperPass( - reinterpret_cast(TM)); + MachineModuleInfoWrapperPass *MMIWP = new MachineModuleInfoWrapperPass(TM); TM->addPassesToEmitFile(PM, OS, nullptr, TT.isNVPTX() ? CodeGenFileType::AssemblyFile : CodeGenFileType::ObjectFile,